Design and Performance Measure of 5.4 GHZ CMOS Low Noise Amplifier Using Current Reuse Technique in 0.18μm Technology

Shankar, Subramaniam; dhas, M. Davidson Kamala

doi:10.1016/j.procs.2015.03.192

Cited by 14 publications

(6 citation statements)

References 13 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Radio frequency (RF) systems and circuits are key elements in various application domains such as mobile wireless communication, wireless local area network applications, mobile cellular, etc. [9,37].…”

Section: On the Modelling Of Low-noise Amplifiers' (Lnas) Performancesmentioning

confidence: 99%

Metamodelling Techniques for the Optimal Design of Low-Noise Amplifiers

et al. 2020

View full text Add to dashboard Cite

In this article we deal with the optimal sizing of low-noise amplifiers (LNAs) using newly proposed metamodeling techniques. The main objective is to construct metamodels of main performances of the LNAs (namely, the third intercept point (IIP3), the scattering parameters (Sij), and the noise figure (NF)) and use them inside an optimization kernel for maximizing the circuits’ performances. The kriging surrogate modelling technique is used for constructing these models. The particle swarm optimization (PSO) technique is considered as the optimization metaheuristic. Two CMOS amplifiers are considered: a UMTS LNA and a multistandard LNA. Obtained results show that, at the considered working frequencies, the first LNA exhibits at 2.14 GHz a noise figure of 1.30 dB, an S21 of 16.01 dB, an S11 of −12.60 dB, and an IIP3 of 8.30 dBm. At 2 GHz, the second LNA has a noise figure of 1.24 dB, an S21 of 17.16 dB, an S11 of −13.74 dB, and an IIP3 of 4.30 dBm. Comparisons between results obtained using the constructed models and those of the simulation are presented to show the perfect agreement between them.

show abstract

Section: On the Modelling Of Low-noise Amplifiers' (Lnas) Performancesmentioning

confidence: 99%

Metamodelling Techniques for the Optimal Design of Low-Noise Amplifiers

et al. 2020

View full text Add to dashboard Cite

show abstract

“…A CS-CS Current reuse LNA [4] is proposed. This proposed work involves the design of LNA with common source topology with current reuse technique as shown in fig 3.…”

Section: Fig 2 Common Gate Topologymentioning

confidence: 99%

Single Stage 180nm CMOS Low Noise Amplifier Topologies and Optimization Algorithms for S Band Frequency

D*¹,

Kavya²

2019

IJRTE

View full text Add to dashboard Cite

Low Noise Amplifier (LNA) plays an important role in radio receivers. It mainly determines the system noise and intermodulation behavior of overall receiver. LNA design is more challenging as it requires high gain, low noise figure, good input and output matching and unconditional stability. Further, designing a Low noise Amplifier requires active device selection, amplifier topology, optimization algorithms for superlative results. Hence this paper presents performance analysis of CMOS LNA based on different topologies and optimization algorithms for 180nm RF CMOS design in S band frequency. Here the best results, various limitations in each topology are reviewed and required specifications are determined in each designing. Further this best topology is used for designing LNA circuit which could be used in Indian Regional Navigation Satellite System (IRNSS) applications in dual band frequency.

show abstract

“…Given this perspective and the aim of minimizing power usage, various techniques have been explored in the current state of the art. The current-reuse (CR) technique, as documented in [11,12], enables the sharing of the DC current among transistors, thereby reducing power consumption without compromising gain. However, it is important to note that this technique is the most advantageous for applications requiring higher voltage.…”

Section: Introductionmentioning

confidence: 99%

Artificial Neural Network Modeling of a CMOS Differential Low-Noise Amplifier Using the Bayesian Regularization Algorithm

Subburaman,

Thangaraj,

Balu

et al. 2023

Sensors

View full text Add to dashboard Cite

The purpose of this communication is to present the modeling of an Artificial Neural Network (ANN) for a differential Complementary Metal Oxide Semiconductor (CMOS) Low-Noise Amplifier (LNA) designed for wireless applications. For satellite transponder applications employing differential LNAs, various techniques, such as gain boosting, linearity improvement, and body bias, have been individually documented in the literature. The proposed LNA combines all three of these techniques differentially, aiming to achieve a high gain, a low noise figure, excellent linearity, and reduced power consumption. Under simulation conditions at 5 GHz using Cadence, the proposed LNA demonstrates a high gain (S21) of 29.5 dB and a low noise figure (NF) of 1.2 dB, with a reduced supply voltage of only 0.9 V. Additionally, it exhibits a reflection coefficient (S11) of less than −10 dB, a power dissipation (Pdc) of 19.3 mW, and a third-order input intercept point (IIP3) of 0.2 dBm. The performance results of the proposed LNA, combining all three techniques, outperform those of LNAs employing only two of the above techniques. The proposed LNA is modeled using PatternNet BR, and the simulation results closely align with the results of the developed ANN. In comparison to the Cadence simulation method, the proposed approach also offers accurate circuit solutions.

show abstract

Design and Performance Measure of 5.4 GHZ CMOS Low Noise Amplifier Using Current Reuse Technique in 0.18μm Technology

Cited by 14 publications

References 13 publications

Metamodelling Techniques for the Optimal Design of Low-Noise Amplifiers

Metamodelling Techniques for the Optimal Design of Low-Noise Amplifiers

Single Stage 180nm CMOS Low Noise Amplifier Topologies and Optimization Algorithms for S Band Frequency

Artificial Neural Network Modeling of a CMOS Differential Low-Noise Amplifier Using the Bayesian Regularization Algorithm

Contact Info

Product

Resources

About