2018 5th International Conference on Information Technology, Computer, and Electrical Engineering (ICITACEE) 2018
DOI: 10.1109/icitacee.2018.8576978
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Design and Performance Test of Three Phased Synchronous Reference Frame-Phase Locked Loop (SRF-PLL) using DSPIC30F4011

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Cited by 7 publications
(2 citation statements)
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“…When a symmetrical fault occurs on the grid, conventional synchronous reference frame phase‐locked loop (SRF–PLL) can be used. The SRF–PLL is one of the most basic and common phase‐locked loops, which controls the q‐axis component u q of the parallel dot voltage to be 0 in the dq coordinate system to achieve phase‐locking, and the structure is shown in Figure 3 [33].…”
Section: Influence Of the Performance Of The Pll On Transformer Diffe...mentioning
confidence: 99%
“…When a symmetrical fault occurs on the grid, conventional synchronous reference frame phase‐locked loop (SRF–PLL) can be used. The SRF–PLL is one of the most basic and common phase‐locked loops, which controls the q‐axis component u q of the parallel dot voltage to be 0 in the dq coordinate system to achieve phase‐locking, and the structure is shown in Figure 3 [33].…”
Section: Influence Of the Performance Of The Pll On Transformer Diffe...mentioning
confidence: 99%
“…71, in red, that exponentially decays to zero, which, when is close to zero, means that the perturbation is over. Therefore, the algorithm goes to S3 only when 𝑎𝑣𝑔(|𝑒|) is a given threshold, 𝑎𝑣𝑔(|𝑒|) < 𝑒 𝑜 .…”
mentioning
confidence: 99%