Design and Power Analysis of 16×16 SRAM Array Employing 7T I-LSVL

Kumar, C. S. Hemanth; Kariyappa, B S

doi:10.1109/rteict42901.2018.9012414

2018 3rd IEEE International Conference on Recent Trends in Electronics, Information &Amp; Communication Technology (RTEICT) 2018

DOI: 10.1109/rteict42901.2018.9012414

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Design and Power Analysis of 16×16 SRAM Array Employing 7T I-LSVL

C. S. Hemanth Kumar¹,

B S Kariyappa²

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Design and Power Analysis of 16×16 SRAM Array Employing 7T I-LSVL

Cited by 1 publication

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