Design and realization of (7,4) Hamming code channel encoder trainer using Arduino Mega 2560

Abstract

Channel encoder is a part of transmitter block in a digital communication system which is capable of protecting information data from errors by adding parity bits from bits of information. The channel encoder receives bits of information from the source encoder and produces a new code called the codeword. Hamming code is one of the coding mechanisms used to protect information data from errors, with the ability to correct an error. This study explains the design of (7.4) Hamming encoder code channel trainer by using Arduino Mega 2560. The purpose of this research is producing a product that synchronizes a theory with the realization of how the channel encoder blocks work. Important parameters in the encoder channel are information bits, matrix generator, and parity bits. The form of the matrix generator affects the parity bits and the generated codeword. Therefore, the trainer is made and designed that can be used in the form of different matrix generator and qualify of (7.4) Hamming code channel encoder. This trainer is made in two stages: the simulation stage using Proteus 8 Professional and the hardware manufacturing stage. The results showed that the trainers worked in accordance with the theory (7.4) Hamming code channel encoder.

A novel Ethernet based processing system for remote source harmonic detection

“…This work uses the ATmega (8-bit) that is installed in the Arduino Mega 2560 board with the addition of Ethernet Shield 2, the board contains a successive approximation register/analog to digital converter (SAR ADC) (10-bit) with a 10 khz sampling rate [2]- [4], [24]. The Ethernet Shield 2 board is added to the system to provide a wireless data link between the two parts of the network [9], [25].…”

Error detection and correction implementation for computer networks using Arduino

“…The important role of error detection and correction has led researchers to develop a large (8,4) expanded hamming code known as Single Error Correcting Double Error Detecting (SEC-DED) code which can detect two errors and correct only one error. This design can increase the system's noise immunity to maximize data reception without errors.…”

“…The suggested architectures are implemented and synthesized in CADENCE [45 nm technology] for Application Specific Integrated Circuit (ASIC) and Field Programmable Gate Array FPGA (Virtex-6 family) [7] . N Karostiani and A B Pantjawati in [8] designing a (7,4) Hamming code encoder trainer. The trainer was developed with various matrix generators to create code words in the channel encoder.…”