2016
DOI: 10.1016/j.vlsi.2016.06.004
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Design and simulation of an ultra-low power high performance CMOS logic: DMTGDI

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Cited by 16 publications
(1 citation statement)
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“…Our half adder scheme is shown in figure 10. The full adder extends the concept of the half adder by providing an additional carry-in (C in ) input as described in [37]. It adds three single-digit binary numbers, two inputs and a carry-in bit.…”
Section: One-bit Half Adder and Full Addermentioning
confidence: 99%
“…Our half adder scheme is shown in figure 10. The full adder extends the concept of the half adder by providing an additional carry-in (C in ) input as described in [37]. It adds three single-digit binary numbers, two inputs and a carry-in bit.…”
Section: One-bit Half Adder and Full Addermentioning
confidence: 99%