Design and standalone characterisation of a capacitively coupled HV-CMOS sensor chip for the CLIC vertex detector

Kremastiotis, I.; Ballabriga, R.; Campbell, M.; Dannheim, D.; Fiergolski, A.; Hynds, D.; Kulis, Szymon; Perić, I.

doi:10.1088/1748-0221/12/09/p09012

Cited by 12 publications

(11 citation statements)

References 8 publications

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“…CLICpix2 prototypes have been glued to C3PD sensors [11], a second-generation active sensor designed in an AMS 180 nm HV-CMOS process with a matching pixel pitch of 25 µm × 25 µm. A cross-section of such an assembly is shown in Figure 4.…”

Section: Capacitively Coupled Detectorsmentioning

confidence: 99%

Technologies for future vertex and tracking detectors at CLIC

Spannagel

2019

Nuclear Instruments and Methods in Physics Research Section A:

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CLIC is a proposed linear e + e − collider with center-of-mass energies of up to 3 TeV. Its main objectives are precise top quark and Higgs boson measurements, as well as searches for Beyond Standard Model physics. To meet the physics goals, the vertex and tracking detectors require not only a spatial resolution of a few micrometers and a very low material budget, but also timing capabilities with a precision of a few nanoseconds to allow suppression of beam-induced backgrounds.Different technologies using hybrid silicon detectors are explored for the vertex detectors, such as dedicated readout ASICs, small-pitch active edge sensors as well as capacitively coupled High-Voltage CMOS sensors. Monolithic sensors are considered as an option for the tracking detector, and a prototype using a CMOS process with a high-resistivity epitaxial layer is being designed. Different designs using a silicon-on-insulator process are under investigation for both vertex and tracking detector.All prototypes are evaluated in laboratory and beam tests, and newly developed simulation tools combining Geant4 and TCAD are used to assess and optimize their performance. This contribution gives an overview of the R&D program for the CLIC vertex and tracking detectors, highlighting new results from the prototypes.

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Section: Capacitively Coupled Detectorsmentioning

confidence: 99%

Technologies for future vertex and tracking detectors at CLIC

Spannagel

2019

Nuclear Instruments and Methods in Physics Research Section A:

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“…The detector devices are placed on application specific chipboards. Currently, CaRIBOu supports CLICpix2, C3PD [2], FEI4 [3] and H35Demo [3] chipboards. In addition, there is ongoing work on the integration of the SOI-Cracow [4] device.…”

Section: Hardwarementioning

confidence: 99%

A Multi-chip Data Acquisition System Based on a Heterogeneous System-on-Chip Platform

Fiergolski

2018

Springer Proceedings in Physics

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The Control and Readout Inner tracking BOard (CaRIBOu) is a versatile readout system targeting a multitude of detector prototypes. It profits from the heterogeneous platform of the Zynq System-on-Chip (SoC) and integrates in a monolithic device front-end FPGA resources with a back-end software running on a hard-core ARM-based processor. The userfriendly Linux terminal with the pre-installed DAQ software is combined with the efficiency and throughput of a system fully implemented in the FPGA fabric. The paper presents the design of the SoC-based DAQ system and its building blocks. It also shows examples of the achieved functionality for the CLICpix2 readout ASIC.Abstract. The Control and Readout Inner tracking BOard (CaRIBOu) is a versatile readout system targeting a multitude of detector prototypes. It profits from the heterogeneous platform of the Zynq System-on-Chip (SoC) and integrates in a monolithic device front-end FPGA resources with a back-end software running on a hard-core ARM-based processor. The user-friendly Linux terminal with the pre-installed DAQ software is combined with the efficiency and throughput of a system fully implemented in the FPGA fabric. The paper presents the design of the SoC-based DAQ system and its building blocks. It also shows examples of the achieved functionality for the CLICpix2 readout ASIC.

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“…The results of the standalone characterisation using bare chips have been reported in [8]. Apart from the internal test pulse injection, the bare chips have been measured using a 55 Fe source.…”

Section: Measurements With Bare C3pd Chipsmentioning

confidence: 99%

“…In addition, the rise time has to be fast enough to ensure that the charge will be fully integrated by the CLICpix2 preamplifier, and the power consumption needs to be kept at a reasonably low level. This calibration is similar to the one performed for the bare C3PD chip [8], this time taking into account the additional load resulting from having the sensor chip capacitively coupled to the readout ASIC. Figure 8 presents some example plots of the DAC scans that were performed in order to optimise the C3PD operating point for the capacitively coupled assembly.…”

Section: Calibration Using Test Pulsesmentioning

confidence: 99%

“…Other characteristics of the front-end, such as gain, rise time and power consumption are within the variations observed during the characterisation of bare C3PD chips. Measured, as well as simulated, values from the standalone characterisation of bare chips (before receiving assemblies with CLICpix2) are presented in [8]. …”

Section: Calibration Using Test Pulsesmentioning

confidence: 99%

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Characterisation of capacitively coupled HV/HR-CMOS sensor chips for the CLIC vertex detector

Kremastiotis

2017

J. Inst.

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The capacitive coupling between an active sensor and a readout ASIC has been considered in the framework of the CLIC vertex detector study. The CLICpix Capacitively Coupled Pixel Detector (C3PD) is a High-Voltage CMOS sensor chip produced in a commercial 180 nm HV-CMOS process for this purpose. The sensor was designed to be connected to the CLICpix2 readout chip. It therefore matches the dimensions of the readout chip, featuring a matrix of 128 × 128 square pixels with 25 µm pitch. The sensor chip has been produced with the standard value for the substrate resistivity (∼ 20 Ωcm) and it has been characterised in standalone testing mode, before receiving and testing capacitively coupled assemblies. The standalone measurement results show a rise time of ∼ 20 ns for a power consumption of 5 µW/pixel. Production of the C3PD HV-CMOS sensor chip with higher substrate resistivity wafers (∼ 20, 80, 200 and 1000 Ωcm) is foreseen. The expected benefits of the higher substrate resistivity will be studied using future assemblies with the readout chip.

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Design and standalone characterisation of a capacitively coupled HV-CMOS sensor chip for the CLIC vertex detector

Cited by 12 publications

References 8 publications

Technologies for future vertex and tracking detectors at CLIC

Technologies for future vertex and tracking detectors at CLIC

A Multi-chip Data Acquisition System Based on a Heterogeneous System-on-Chip Platform

Characterisation of capacitively coupled HV/HR-CMOS sensor chips for the CLIC vertex detector

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