Design and Switching Characteristics of Flip-Chip GaN Half-Bridge Modules Integrated with Drivers

Abstract

Half-bridge modules with integrated GaN high electron mobility transistors (HEMTs) and driver dies were designed and fabricated in this research. Our design uses flip-chip technology for fabrication, instead of more generally applied wire bonding, to reduce parasitic inductance in both the driver-gate and drain-source loops. Modules were prepared using both methods and the double-pulse test was applied to evaluate and compare their switching characteristics. The gate voltage (Vgs) waveform of the flip-chip module showed no overshoot during the turn-on period, and a small oscillation during the turn-off period. The probabilities of gate damage and false turn-on were greatly reduced. The inductance in the drain-source loop of the module was measured to be 3.4 nH. The rise and fall times of the drain voltage (Vds) were 12.9 and 5.8 ns, respectively, with an overshoot of only 4.8 V during the turn-off period under Vdc = 100 V. These results indicate that the use of flip-chip technology along with the integration of GaN HEMTs with driver dies can effectively reduce the parasitic inductance and improve the switching performance of GaN half-bridge modules compared to wire bonding.

Comparison of the parasitic impedances from the drain‐source path of power transistor packages at up to 2 GHz

“…17 Therefore, a suitable way to improve the parasitic inductances is to optimize the power transistor package. There have been preliminary works on the switching performance of GaN HEMT flip-chip packages, 18,19 but they are limited to the best of our knowledge to experimental demonstrations and only indirectly incorporate the parasitic inductances of the transistor package. Here, we show the evolution of the parasitic impedances directly through simulations of the drain source path from four generations of packages, already employed (package 1 and 2) and some that will be employed in future (package 3 and 4) at Infineon.…”