Design And Synthesis Of Array Structured Telecommunication Processing Applications

Meyer, W.; Seawright, Andrew; Tada, F.

doi:10.1109/dac.1997.597196

Cited by 6 publications

(7 citation statements)

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“…These techniques resulted in hardware machine implementations that were comparable or superior to those synthesized using conventional methods and which could be scaled to very large (thousands of bits) FSMs. This work was the progenitor of the Synopsys Protocol Compiler [11] and pyPBS [9]. Drawing from a general construction method, pyPBS added several powerful language constructs necessary for specifying complex control operations such as tail-recursion and non-local observation.…”

Section: Related Workmentioning

confidence: 99%

Extensible control architectures

Hoover

Brewer

Sherwood

2006

Proceedings of the 2006 International Conference on Compilers, Architecture and Synthesis for Embedded Systems

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Architectural advances of modern systems has often been at odds with control complexity, requiring significant effort in both design and verification. This is particularly true for sequential controllers, where machine complexity can quickly surpass designer ability. Traditional solutions to this problem require elaborate specifications that are difficult to maintain and extend. Further, the logic generated from these specifications bares no resemblance to the intended behavior and often fails to meet design performance constraints. In the process of designing a multi-threaded, dynamically-pipelined microcontroller, we encountered a number of common difficulties that arise from the inadequacies of traditional pipeline design methodologies. Through the use of a novel nondeterministic finite automata (NFA) specification model, we were able to implement an extensible control structure with minimal design effort. In this paper we present a viable pipeline controller specification methodology using the pyPBS language, which enables minimal effort control partitioning and compact behavioral representation. The structure of the language encourages design decisions that promote efficient modular constructions which can be easily integrated and extended. We present an overview of the our methodology including background on the pyPBS synthesis model, an architectural overview of our multi-threaded microcontroller, and implementation details for the control structure of the design including the complete control specifications. In addition, we show that the applicative nature of the pyPBS language allows for addition of a multi-cycle multiplication unit with minimal effort.

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Section: Related Workmentioning

confidence: 99%

Extensible control architectures

Hoover

Brewer

Sherwood

2006

Proceedings of the 2006 International Conference on Compilers, Architecture and Synthesis for Embedded Systems

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“…It is based on previous work by Seawright and Brewer, and later Crews, on logic synthesis from grammatical productions [Sea94,Cre96]. Protocol Compiler was first described in [Sea96] and an application for SDH/SONET is shown in [Mey97]. The design environment consists of entry, debugging support (by means of annotating simulation results back onto the source), protocol synthesis, and HDL generation (Both VHDL and Verilog are supported).…”

Section: Related Workmentioning

confidence: 99%

“…The Protocol Compiler language is conceptually higher than RTL and, together with protocol synthesis and intuitive debugging capabilities, is the key element resulting in a productivity gain for design and verification of controllers. Due to limited space please see [Sea96,Mey97] for a detailed description.…”

Section: Related Workmentioning

confidence: 99%

Design of a SPDIF receiver using protocol compiler

Holtmann

Blinzer

1998

Proceedings of the 35th Annual Conference on Design Automation Conference - DAC '98

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This paper describes the design of a receiver for the digital audio signal SPDIF used by CD-ROM players. The design was done with Protocol Compiler, a high-level synthesis tool for the design of structured data stream processing controllers. Compared to traditional RTL design, ProtocolCompiler makes entry, debugging, and re-use easier. Design time was cut by factor 2 while the results in terms of area and delay are competitive.

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“…The system accomplishes this through describing specifications using only synchronization, the transmission data structure, and the Transport Processing Action (TPA) for the transmission data. Some systems have a similar input form using the frame structure and action for system functions [14] [15]. However, the designers must recognize clock cycles and define tool constraints for activation timing.…”

Section: Related Workmentioning

confidence: 99%