Design and Synthesis of LFSR based Random Number Generator

Durga, R Sri; Rashmika, C K; Madhumitha, Oruganti N V; Suvetha, D G; Tanmai, Bandaru; Mohankumar, N.

doi:10.1109/icssit48917.2020.9214240

Cited by 22 publications

(7 citation statements)

References 8 publications

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“…8a. A PRBS bit stream can be generated by connecting the DFFs using a LFSR configuration 50,51 . So, as each bit traverses through each flop, a certain bit delay is introduced until the data reaches last flop.…”

Section: Realization Of Leaf Cells Using Poc-dg-ajltfetmentioning

confidence: 99%

Implementation and performance analysis of QPSK system using pocket double gate asymmetric JLTFET for satellite communications

Boggarapu

Lakshmi

2023

Sci Rep

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This work is intended to design a quadrature phase shift keying (QPSK) system starting from the device design, characterization and optimization which is then followed by the circuit level implementation and finally the system level configuration. Tunnel Field Effect Transistor (TFET) technology came into existence because of the inability of CMOS (Complementary Metal Oxide Semiconductor) to produce reduced leakage current (Ioff) in the subthreshold regime. With the effects of scaling and requirement of high doping concentrations, TFET is not capable to produce stable reduction in Ioff due to the variation in ON and OFF current. To improve the switching ratio of the current and to obtain good subthreshold swing (SS) by overcoming the limitations of junction TFET, a new device design is proposed for the first time in this work. A pocket double gate asymmetric Junction less TFET (poc-DG-AJLTFET) structure has been proposed in which uniform doping is used to eliminate the junctions and a pocket of length 2 nm made of Silicon–Germanium (SiGe) material has been introduced to improve the designed structure performance in the weak inversion region and increase the drive current (ION). The work function has been tuned to produce the best results for poc-DG-AJLTFET and with our proposed poc-DG-AJLTFET, effects of interface traps are eliminated as against conventional JLTFET structures. The notion that low-threshold voltage device yields high IOFF has been proved wrong with our poc-DG-AJLTFET design, as it produced low threshold voltage with lower IOFF which reduced the power dissipation. Numerical results show that drain induced barrier lowering (DIBL) of 2.75 mV/V is achieved which could be less than 35 times required for short channel effects to be minimum. In terms of gate to drain capacitance (Cgd), it is found that ~ 103 reduction which greatly improves device inertia to internal electrical interference. Also, improvement in transconductance is achieved by 104 times, 103 times improvement in ION/IOFF ratio, and 400 times higher unity gain cutoff-frequency (ft) which would be required by all communication systems. The Verilog models of the designed device are used to construct the leaf cells of quadrature phase shift keying (QPSK) system and the implemented QPSK system is taken as a key evaluator in the performance evaluation in terms of propagation delay and power consumption of poc-DG-AJLTFET in modern satellite communication systems.

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Section: Realization Of Leaf Cells Using Poc-dg-ajltfetmentioning

confidence: 99%

Implementation and performance analysis of QPSK system using pocket double gate asymmetric JLTFET for satellite communications

Boggarapu

Lakshmi

2023

Sci Rep

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“…Linear feedback shift registers (LFSR) is widely employed for key stream generator, that have the virtue of perfect 0 − 1 statistical distribution, two-valued auto correlation, large period, low implementation cost with ready analysis using algebraic technique [9,15,20]. This device is mostly treated as the building blocks of many sequence generators from last two decades [2,3,7,19]. A LFSR of a given size n is capable of producing maximal sequence (m − sequence) by passing through every non−zero state once and only once to give the period N = 2 n − 1, excluding the all−zero state, make a good choice for evolving a stream ciphers.…”

Section: Introductionmentioning

confidence: 99%

The Improvement of Period of Pseudo Random Number Sequence: an Algebraic Approach

Ghosh

2023

Preprint

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Linear feedback shift registers are the fundamental structure of pseudo random number generators that are used in formation of channel key. Many methods were proposed for determining linear recurring sequences generated by Linear Feedback Shift Registers to enhance the period. In view of large scale application of this sequence in security and privacy, a clocked controlled linear feedback shift register has been introduced, known as dynamic linear feedback shift register. In this article, we emphasis on dynamic linear feedback shift register scheme using combinatorial design having constant block length and algebraic structure to enhance the period. Such sequence has the vulnerability from attack. Our proposal for designing dynamic linear feedback shift register involves primitive polynomial over a finite fields of prime power. A counter example shown the practical implication of our theory that improve the period of the sequence than existing scheme. Finally an effort was thru on properties of the generated sequence in terms of security aspect. Mathematics Subject Classification Code[2020]: 68W30, 12L15.

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“…Nowadays, the Linear Feedback Shifted Register (LFSR) is a simple and widely used algorithm for implementing hardware circuits. References [9][10][11][12][13][14] used the LFSR algorithm to implement a random number generator on FPGA. Among them, the literature [9] proposes a new architecture based on Leap-Ahead LFSR, namely Transformed Leap (TL) LFSR, which reduces the autocorrelation problems existing in Leap-Ahead LFSR.…”

Section: Introductionmentioning

confidence: 99%

“…Among them, the literature [9] proposes a new architecture based on Leap-Ahead LFSR, namely Transformed Leap (TL) LFSR, which reduces the autocorrelation problems existing in Leap-Ahead LFSR. The literature [12] proposed a random number generator based on LFSR, which contains a polynomial modulator to increase the unpredictability of the random number generator. However, the LSFR algorithm has a significant drawback: it can only produce one bit of random number at a time during one clock cycle, resulting in poor output efficiency of the random number generator.…”

Section: Introductionmentioning

confidence: 99%

Improved Mersenne Twister random number generator based on FPGA

Liu,

Zhong,

Huan

et al. 2023

5th International Conference on Information Science, Electrical, and Automation Engineering (ISEAE 2023)

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With the development of the field of scientific computing, the rapid generation of high-quality random numbers has become a crucial aspect of research. However, traditional methods are often insufficient in meeting the efficiency and quality requirements of random number generation. In this paper, we propose an improved version of the Mersenne Twister algorithm, implemented on the FPGA platform. By optimizing the characteristic polynomial in the Transform module, the randomness and uniformity of the Mersenne Twister (MT) algorithm are enhanced. The core modules of the algorithm are realized through a parallel structure one the FPGA, with the AXI4-Stream data bus utilized as the protocol for data interaction with peripherals. Finally, the quality of the random numbers by the designed generator is tested, and the results demonstrate that it can efficiently produce high-quality, uniformly distributed random numbers. These numbers are well-suited for applications that require the rapid generation of large quantities and high-quality random numbers, such as Monte Carlo simulations.

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Design and Synthesis of LFSR based Random Number Generator

Cited by 22 publications

References 8 publications

Implementation and performance analysis of QPSK system using pocket double gate asymmetric JLTFET for satellite communications

Implementation and performance analysis of QPSK system using pocket double gate asymmetric JLTFET for satellite communications

The Improvement of Period of Pseudo Random Number Sequence: an Algebraic Approach

Improved Mersenne Twister random number generator based on FPGA

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