Design and Technology Co-optimization for Investigating Power, Performance, Area and Cost Trade-Offs in FinFET Technologies

Kumbar, Vijayalaxmi; Raut, Vaishali

doi:10.1007/978-981-16-7985-8_64

Cited by 2 publications

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“…The SG-FinFET and IG-FinFET are often recognized as 3-terminal (3T) and four-terminal (4T) devices[31] [1]. The rear and front gates of SG FinFETs are both physically shorted, whereas the gates of IG FinFETs are physically isolated[45]. Therefore, in SG-FinFETs, both gates are employed to control the channel electrostatics.…”

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A Comparative Analysis of FinFET Based SRAM Design

Kumbar¹,

Waje²

2022

IJEER

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FinFETs are widely used as efficient alternatives to the single gate general transistor in technology scaling because of their narrow channel characteristic. The width quantization of the FinFET devices helps to reduce the design flexibility of Static Random Access Memory (SRAM) and tackles the design divergence between stable, write and read operations. SRAM is widely used in many medical applications due to its low power consumption but traditional 6T SRAM has short channel effect problems. Recently, to overcome these problems various 7T, 9T, 12T, and 14T SRAM architectures are designed using FinFET. This article provides a comprehensive survey of various designs of SRAM using FinFET. It offers a comparative analysis of FinFET technology, power consumption, propagation delay, power delay product, read and write margin. Additionally, the article presents the simulation of the 5T and 6T SRAM design using CMOS and FinFET for 14 nm technology using Microwind 3.8 simulation tool. The outcomes of the proposed SRAM design are compared with several recent designs based on power, delay, and, and various stability analysis parameters such as read, write and hold noise margin. Finally, the article discusses the challenges in SRAM design using FinFET and provides the future direction for optimization of accuracy, area, speed, delay, and cost of the FinFET-based SRAMs.

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confidence: 99%