Design and Test of a 175-Mb/s, Rate-1/2 (128,3,6) Low-Density Parity-Check Convolutional Code Encoder and Decoder

An efficient multi-rate Low-Density Parity-Check Convolutional Code decoder will be present in this paper. We will introduce layered decoding algorithm into LDPC-CC decoding. Simulation results shows that our method can achieve better performance than the original brief propagation algorithm with less processors. Besides a new ASIC architecture which adopt proposed algorithm and can support all code rate (1/2, 2/3, 3/4, 4/5) of the LDPC-CC code in IEEE 1901 is proposed. Based on SMIC 130 nm CMOS process, our decoder attaints a maximum throughput of 333.3 Mb/s at 200 MHz. The core area is 3.55 mm 2 with 10 processors. The average power consumption is 262 mW at code rate 4/5 and 200 MHz. The VLSI result shows that our decoder is both memory efficient and area efficient.

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“…Then decoder in [10], [11] utilizes these concepts directly. It's register-based and lots of registers are used to implement the FIFO.…”

Section: Vlsi Implementmentioning

confidence: 99%

An efficient multi-rate LDPC-CC decoder with layered decoding algorithm

Chen

Zhou

Huang

et al. 2013

2013 IEEE International Conference on Communications (ICC)

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“…In [17], it used the BCH based DEC-TED code to protect L2-chache from soft errors. In [10], a high performance 2D ECC encoding technique with low VLSI overhead and strong correcting capability is introduced to protect the memory system from soft errors, it investigates the design of the high performance multidimensional ECC for dynamic memory systems. In general, ECC is effective to correct undesired soft errors, while few works introduce it into the out-of-order pipeline.…”

Section: Related Workmentioning

confidence: 99%

“…Furthermore, it can recover the protected data from a number of errors [8]. There are some typical ECC, such as hamming code [9] applied in DRAM controllers, SEC-DED code used in memory systems, the parity check code [10] used in storage systems. The advantage of ECC is that it can correct the faults within its capacity instead of re-executing the fault instructions.…”

Section: Introductionmentioning

confidence: 99%

A Fault-Tolerant Architecture with Error Correcting Code for the Instruction-Level Temporal Redundancy

Yan

Dai

Chen

2012

IEICE Trans. Inf. & Syst.

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SUMMARYSoft error has become an increasingly significant concern in modern micro-processor design, it is reported that the instruction-level temporal redundancy in out-of-order cores suffers an performance degradation up to 45%. In this work, we propose a fault tolerant architecture with fast error correcting codes (such as the two-dimensional code) based on double execution. Experimental results show that our scheme can gain back IPC loss between 9.1% and 10.2%, with an average around 9.2% compared with the conventional double execution architecture.

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“…If is a square matrix, i.e., , then is an identity matrix and is the unique inverse of . If , then contains columns corresponding to free variables (see (12) in Appendix B). To ensure that all the free variables are set to zero, we insert rows of zeros to the corresponding locations of , and get a matrix, which is the right inverse of : .…”

Section: ) Step 1: Determine the Termination Lengthmentioning

confidence: 99%

“…A detailed comparison of code performance and decoding complexity between LDPC-CCs and LDPC-BCs can be found in [11]. Both application-specific integrated circuit (ASIC) and field-programmable gate array implementations of LDPC-CC decoders have been reported [12], [13]. Compared to LDPC-BCs, one major disadvantage of LDPC-CCs is that the coded sequence needs to be properly terminated when applied to finite-length data frames [14].…”

mentioning

confidence: 99%

Efficient Implementation of Low-Density Parity-Check Convolutional Code Encoders With Built-In Termination

Chen

Brandon

Bates

et al. 2008

IEEE Trans. Circuits Syst. I

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Low-density parity-check convolutional codes (LDPC-CCs) have demonstrated comparable error-correcting performance to LDPC block codes (LDPC-BCs). However, the LDPC-CC encoder requires termination when applied to finite-length data frames to ensure that the trailing information bits are fully protected. In this paper, the LDPC-CC encoder design is investigated, and a novel termination scheme is proposed. Starting from any encoder state, the proposed scheme is capable of generating a termination sequence in hardware without padding, thus minimizing the rate loss due to termination. A high-speed architecture for LDPC-CC encoders with built-in termination is proposed. Synthesis results for LDPC-CCs of code memory size up to 512 demonstrate maximum encoding throughputs of around 1 Gb/s for a 90-nm CMOS technology. The implementation cost for such encoders is shown to be reasonably low for average-sized LDPC-CCs.

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Design and Test of a 175-Mb/s, Rate-1/2 (128,3,6) Low-Density Parity-Check Convolutional Code Encoder and Decoder

Cited by 16 publications

References 18 publications

An efficient multi-rate LDPC-CC decoder with layered decoding algorithm

An efficient multi-rate LDPC-CC decoder with layered decoding algorithm

A Fault-Tolerant Architecture with Error Correcting Code for the Instruction-Level Temporal Redundancy

Efficient Implementation of Low-Density Parity-Check Convolutional Code Encoders With Built-In Termination

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