This paper presents the design and automatic system verification of digital baseband for Ultra High Frequency (UHF) radio frequency identification (RFID) tag, which is complied with a modified ISO 18000-6C protocol. Module-reuse approach and low power techniques are applied in the digital baseband to reduce the power consumption. And a novel verification strategy is discussed, which decreases the verification cycle greatly via function test mode and coverage test mode, and generates testcases automatically by using coverage-driven random-based approach. The strategy has many merits, such as a hierarchical architecture for reuse, inspecting low power design though assertion, locating bugs accurately, and linking C++ via direct programming interface (DPI). The tag chip is designed in a 0.18um CMOS process with a size of 89234 um 2. Simulation results verify the efficiency of the proposed methods. Index Terms-RFID passive tag baseband, automatic system verification, coverage-driven random-based approach, SystemVerilog, DPI Xin'an Wang received the B.