Design and test of a 50 mK CMOS 16 to 1 multiplexing ASIC for high impedance NbSi TES arrays

Abstract

Achieving high spectral and spatial resolution of wide astrophysical objects in theX-ray band will be the main focus of the future X-ray space telescopes.We explorea new technological solution based on high impedance TES detectors (∼2MΩ)enabling the transfer of the pre-amplification stage to higher temperatures (4 K)and the use of a 50mK CMOS multiplexer to reduce power dissipation at 50 mK.We present the design and first tests of a 50mK CMOS ASIC multiplexing 16high impedance NbSi TES detectors to 1 amplifier with a total power budgetunder 2μW. In parallel of this development, we fabricated 4-by-4 NbSi pixelmatrices to build a complete demonstrator (comprising the detector array, themultiplexing ASIC and the 4K amplification stage). We aim at a multiplexingcycle time of 48μs leaving 3μs for reading-out each high impedance pixel. Themultiplexing ASIC will embed parasitic capacity compensation techniques.