Design and Testing Parallel Prefix Adders using Reconfigurable LFSR in FPGA

Abstract

The main criteria of this paper is to design Reconfigurable Linear Feedback Shift Register (LFSR) for very large scale integration(VLSI) of Integrated Circuit(IC) testing .Comparability to the Automatic Test Equipment(ATE) the Logic Built In Self Test(LBIST) has take into popularity. This logic built which helps in built testing with the help of additional hardware construction indoors the circuit. Thus doesn't contains the test pattern but they generate by the testing circuits. By this can out down the testing cost substantially. LFSR is mostly used as a test pattern generate for IC testing. To improve the fault coverage of IC testing in logic BIST using Reconfigurable LFSR. It is configurable to generate the maximum length of the pattern depending on the feedback polynomial that provide as per requirement. In this paper, the proposed reconfigurable LFSR of four structural represented in modular, standard, hybrid and complete LFSR is simulated in different sizes (8,16,32,64) in Xilinx Spartan 3E with an application of Parallel Prefix Adder (konge stone) of 16-bit.This simulation results shows the increasing of