Design and Validation for FPGA Trust under Hardware Trojan Attacks

Abstract

Field programmable gate arrays (FPGAs) are being increasingly used in a wide range of critical applications including industrial, automotive, medical, and military systems. Since FPGA vendors are typically fabless, it is more economical to outsource device production to off-shore facilities. This introduces many opportunities for the insertion of malicious alterations of FPGA Devices in the foundry, referred to as hardware Trojan attacks, that can cause logical and physical malfunctions during field operation. The vulnerability of these devices to hardware attacks raises serious security concerns regarding hardware and design assurance. In this paper, we present a taxonomy of FPGA-specific hardware Trojan attacks based on activation and payload characteristics along with Trojan models that can be inserted by an attacker. We also present an efficient Trojan detection method for FPGA based on a combined approach of logic-testing and side-channel analysis. Finally, we propose a novel design approach, referred to as Adapted Triple Modular Redundancy (ATMR), to reliably protect against Trojan circuits of varying forms in FPGA devices. We compare ATMR with the conventional TMR approach. The results demonstrate the advantages of ATMR over TMR with respect to power overhead, while maintaining the same or higher level of security and performances as TMR. Further improvement in overhead associated with ATMR is achieved by exploiting reconfiguration and time-sharing of resources.!

Hardware Trojan detection for lightweight ciphers implemented on field‐programmable gate arrays using the replay algorithm

“…In case of a mismatch, the correct result is determined by the voter. TMR impacts performance and increases area, power, and energy 9 . Also, TMR might fail if a HT is embedded in the voter circuit 9 …”

“…TMR impacts performance and increases area, power, and energy 9 . Also, TMR might fail if a HT is embedded in the voter circuit 9 …”

“…HTs could be inserted at any step of the design implementation and typically not detected during testing and verification steps. One of the primary causes of HTs is outsourcing of the design and manufacturing 9 . HTs pose a real threat to applications in many areas, including communications, space, medicine, military, and government 9 …”

“…One of the primary causes of HTs is outsourcing of the design and manufacturing 9 . HTs pose a real threat to applications in many areas, including communications, space, medicine, military, and government 9 …”

“…A sequential HT consists of states, where state transitioning is controlled by predefined events. The number of states and events rarity determine the complexity of the sequential HT 9–11 . Unfortunately, FPGAs are more vulnerable to HTs because of their regular structure, which is easier to reverse‐engineer 12 .…”