Design and validation of a performance and power simulator for PowerPC systems

Shafi, Hazim; Bohrer, Patrick; Phelan, James M.; Rusu, Cosmin; Peterson, James L.

doi:10.1147/rd.475.0641

Cited by 37 publications

(20 citation statements)

References 11 publications

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“…An initial version of this work that dealt primarily with transaction level power estimation for peripherals appeared in [19]. For modeling the processor power we used the instruction/processor architectural event characterization data derived from real hardware simulations of the PowerPC processor core [16]. That data derived in [16] contained the average power for each architectural event in the processor, where an architectural event corresponds to types of instructions (e.g., load/stores, cache misses, arithmetic instructions).…”

Section: General Power Modeling Approachmentioning

confidence: 99%

“…For modeling the processor power we used the instruction/processor architectural event characterization data derived from real hardware simulations of the PowerPC processor core [16]. That data derived in [16] contained the average power for each architectural event in the processor, where an architectural event corresponds to types of instructions (e.g., load/stores, cache misses, arithmetic instructions). In our approach, as the ISS executes instructions, it calls a callback routine at the completion of each instruction.…”

Section: General Power Modeling Approachmentioning

confidence: 99%

“…In our approach, as the ISS executes instructions, it calls a callback routine at the completion of each instruction. At that point, the callback routine checks the type of instruction and adds up the corresponding energy value derived in [16]. Given the total execution time of the code, the system computes the average power consumed by the processor (executing code).…”

Section: General Power Modeling Approachmentioning

confidence: 99%

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Transaction-level modeling for architectural and power analysis of PowerPC and CoreConnect-based systems

Dhanwada

Bergamaschi

Dungan

et al. 2005

Des Autom Embed Syst

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Transaction-Level models have emerged as an efficient way of modeling systemson-chip, with acceptable simulation speed and modeling accuracy. Nevertheless, the high complexity of current architectures and bus protocols make it very challenging to develop and verify such models. This paper presents the transaction-level models developed at IBM for PowerPC and CoreConnect-based systems. These models can be simulated in a SystemC environment for functional verification and power estimation. Detailed transactionbased power models were developed. Comparisons between the simulated models and real hardware resulted in errors below 15% in timing accuracy, and below 11% in power estimation compared against gate-level power. These results demonstrate the efficiency of our transaction-level models for early analysis and design space exploration.

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Section: General Power Modeling Approachmentioning

confidence: 99%

Section: General Power Modeling Approachmentioning

confidence: 99%

Section: General Power Modeling Approachmentioning

confidence: 99%

See 1 more Smart Citation

Transaction-level modeling for architectural and power analysis of PowerPC and CoreConnect-based systems

Dhanwada

Bergamaschi

Dungan

et al. 2005

Des Autom Embed Syst

View full text Add to dashboard Cite

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“…Bohrer et al have studied real webserver workloads from sports, e-commerce, financial, and internet proxy cluster and found that average server utilization varies between 11% and 50% [19]. Low utilization has two causes [3]: to guarantee good performance at periods of peak demands, processing capacity is overprovisioned.…”

Section: Introductionmentioning

confidence: 99%

Energy optimization schemes in cluster with virtual machines

Liao

Jin

2009

Cluster Comput

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Large scale clusters based on virtualization technologies have been widely used in many areas, including the data center and cloud computing environment. But how to save energy is a big challenge for building a "green cluster" recently. However, previous researches, including local approaches, which focus on saving the energy of the components in a single workstation without a global vision on the whole cluster, and cluster-wide energy saving techniques, which can only be applied to homogeneous workstations and specific applications, cannot solve the challenges. This paper describes the design and implementation of a novel scheme, called Magnet, that uses live migration of virtual machines to transfer load among the nodes on a multi-layer ring-based overlay. This scheme can reduce the power consumption greatly by regarding all the cluster nodes as a whole based on virtualization technologies. And, it can be applied to both the homogeneous and heterogeneous servers. Experimental measurements show that the new method can reduce the power consumption by 74.8% over base at most with certain adjustably acceptable overhead. The effectiveness and performance insights are also analytically verified.

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“…Mambo [4] is IBM's full-system simulator which models the PowerPC-based [8] systems, and provides a complete set of simulation tools to help IBM and its partners in pre-hardware development and performance evaluation for future systems [15,1,6,14]. Mambo supports both functional and cycle-accurate simulation modes:…”

Section: Introductionmentioning

confidence: 99%

Parallelization of IBM mambo system simulator in functional modes

Wang

Shen

2008

SIGOPS Oper. Syst. Rev.

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Mambo [4] is IBM's full-system simulator which models PowerPC systems, and provides a complete set of simulation tools to help IBM and its partners in pre-hardware development and performance evaluation for future systems. Currently Mambo simulates target systems on a single host thread. When the number of cores increases in a target system, Mambo's simulation performance for each core goes down. As the so-called "multi-core era" approaches, both target and host systems will have more and more cores. It is very important for Mambo to efficiently simulate a multicore target system on a multi-core host system. Parallelization is a natural method to speed up Mambo under this situation.Parallel Mambo (P-Mambo) is a multi-threaded implementation of Mambo. Mambo's simulation engine is implemented as a user-level thread-scheduler. We propose a multischeduler method to adapt Mambo's simulation engine to multi-threaded execution. Based on this method a corebased module partition is proposed to achieve both high inter-scheduler parallelism and low inter-scheduler dependency. Protection of shared resources is crucial to both correctness and performance of P-Mambo. Since there are two tiers of threads in P-Mambo, protecting shared resources by only OS-level locks possibly introduces deadlocks due to user-level context switch. We propose a new lock mechanism to handle this problem. Since Mambo is an on-going project with many modules currently under development, co-existence with new modules is also important to P-Mambo. We propose a global-lock-based method to guarantee compatibility of P-Mambo with future Mambo modules.We have implemented the first version of P-Mambo in functional modes. The performance of P-Mambo has been evaluated on the OpenMP implementation of NAS Parallel Benchmark (NPB) 3.2 [12]. Preliminary experimental results show that P-Mambo achieves an average speedup of 3.4 on a 4-core host machine.

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Design and validation of a performance and power simulator for PowerPC systems

Cited by 37 publications

References 11 publications

Transaction-level modeling for architectural and power analysis of PowerPC and CoreConnect-based systems

Transaction-level modeling for architectural and power analysis of PowerPC and CoreConnect-based systems

Energy optimization schemes in cluster with virtual machines

Parallelization of IBM mambo system simulator in functional modes

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