Design and Verification of APB IP Core using Different Verification Methodologies

Sahu, Nainsi; Kumar, Ashwni; Kandari, Ritu

doi:10.1109/bharat53139.2022.00040

Cited by 4 publications

(2 citation statements)

References 7 publications

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“…The verification environment is created by combining the various components that conduct certain tasks or operations. Various classes will be built in the verification environment to execute certain tasks, such as creating stimuli, driving, tracking, and so on, and each class will be named after the task [44].…”

Section: Verificationmentioning

confidence: 99%

Development of SRAM-APB protocol interface and verification

Karthikeyan,

Balamurugan,

Rao Namamula

et al. 2023

Eng. Res. Express

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The purpose of this mechanism is to enhance the chip’s internal connections and read/write memory capabilities. The Advanced Microcontroller Bus Architecture (AMBA) is one such shared bus that uses static random-access memory to achieve this goal. As a result, it’s important to weigh a variety of design options before diving into the Verilog description. It’s also important to remember that the system must be designed to accommodate a large number of interoperable modules and memories. The design, on the other hand, starts with fewer modules and a less complicated description and realisation that relies on memory access. ModelSim is used to simulate after the delay has been modelled in Verilog. Since the interface’s static random-access memory uses an APB protocol, its performance may be tested at this stage. In addition, Questasim employs verification modules and System Verilog technologies to guarantee the system’s operation. From the obtained results, the Direct Memory Access (DMA) with SRAM-APB outperforms the alternatives, particularly in frame transmission schemes, with a wire efficiency that is 1.4 times higher and a dynamic energy efficiency that is nearly twice as high as those of conventional configurations.

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Section: Verificationmentioning

confidence: 99%

Development of SRAM-APB protocol interface and verification

Karthikeyan,

Balamurugan,

Rao Namamula

et al. 2023

Eng. Res. Express

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show abstract

“…In general, the main devices, SoC, CPU, and DMA, are connected to multiple slave devices through the AHB bus interconnection matrix. The AHB bus interconnection matrix enables different master devices to access different slave devices simultaneously, realizing parallel transmission of data of multiple master devices [30,31].…”

Section: Basic Architecture Of Universal Socmentioning

confidence: 99%

Design and Implementation of an Efficient Hardware Coprocessor IP Core for Multi-axis Servo Control Based on Universal SoC

et al. 2023

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The multi-axis servo control system has been extensively used in industrial control. However, the applications of traditional MCU and DSP chips in high-performance multi-axis servo control systems are becoming increasingly difficult due to their lack of computing power. Although FPGA chips can meet the computing power requirements of high-performance multi-axis servo control systems, their versatility is insufficient, and the chip is too costly for large-scale use. Therefore, when designing the universal SoC, it is better to directly embed the coprocessor IP core dedicated to accelerating the multi-motor vector control current loop operation into the universal SoC. In this study, a coprocessor IP core that can be flexibly embedded in a universal SoC was designed. The IP core based on time division multiplexing (TDM) technology could accelerate the multi-motor vector control current loop operation according to the hardware–software coordination scheme proposed in this study. The IP was first integrated into a universal SoC to verify its performance, and then the FPGA prototype verification for the SoC was performed under three-axis servo control systems. Secondly, the ASIC implementation of the IP was also conducted based on the CSMC 90 nm process library. The experimental results revealed that the IP had a small area and low power consumption and was suitable for application in universal SoC. Therefore, the cheap and low-power single universal SoC with the coprocessor IP can be suitable for multi-axis servo control.

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