Design and Verification of Asynchronous FIFO with Novel Architecture Using Verilog HDL

Yadlapati, Avinash; Kakarla, Hari Kishore

doi:10.36478/jeasci.2019.159.163

Cited by 9 publications

(4 citation statements)

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“…Compared with synchronous FIFO read and write in the same clock signal, asynchronous FIFO read data and write data in different clock signals, so asynchronous FIFO is mainly applied to realize data transmission between different clock domains or as a data interface of different data widths. Asynchronous FIFO includes four modules: dual port RAM, control module, control module, the clock synchronization module [2].…”

Section: Asynchronous Fifo Basic Modulementioning

confidence: 99%

Asynchronous FIFO Design Based on Verilog

Xu¹

2023

HSET

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With the rapid development of integrated circuits, asynchronous First Input First Output (FIFO) is often used to solve the problem of data transmission across the clock domain. This paper mainly studies the key problem of asynchronous FIFO design - the generation of empty - full signal. To solve this problem, it is necessary to realize the synchronization of signal across the clock domain and convert binary code into gray code to reduce the probability of metastable state. The null and full signals generated by the asynchronous FIFO designed in this paper are false null and false full, but this does not affect the function of the asynchronous FIFO, and will only lose part of the performance. Through Modelsim simulation verification, the designed asynchronous FIFO can realize first-in, first-out of data and correctly generate empty and full signal, which meets the design requirements. The research of this paper is helpful for further application of asynchronous FIFO in data transmission across clock domains.

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Section: Asynchronous Fifo Basic Modulementioning

confidence: 99%

Asynchronous FIFO Design Based on Verilog

Xu¹

2023

HSET

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“…Asynchronous FIFO is generally composed of five core modules, namely: RAM memory module, write control port and write clock synchronization module, read control port and read clock synchronization module [2]. The design framework was shown in figure 1.…”

Section: Asynchronous Fifo Designmentioning

confidence: 99%

Design and optimization of asynchronous FIFO based on Verilog HDL

Cheng

2023

Second International Conference on Statistics, Applied Mathematics, and Computing Science (CSAMCS 2022)

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SoC system is a new chip design scheme, which can integrate a large number of functions in the same chip, so it has high requirements for asynchronous data transmission between different modules. Asynchronous FIFO is an efficient and reliable data transmission mode, which is often used as a data matcher in SoC system. This paper, through the modular design, layer by layer construction method, designs a asynchronous FIFO, and for the common problems to optimize, makes its performance more reliable. And according to the simulation results, it can be judged that this design can effectively and reliably carry out asynchronous data transmission.

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“…The data link layer is responsible for 8B/10B decoding/encoding and scrambling/descrambling operations. The physical layer incorporates serializers/deserializers that facilitate the serialization and deserialization of data at the line rate on high-speed transceivers [3] .…”

Section: Overview Of Jesd204bmentioning

confidence: 99%

High-speed ADC interface design based on JESD204B protocol

Rui,

Jianyu,

Chunhua

et al. 2023

Fourth International Conference on Signal Processing and Computer Science (SPCS 2023)

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Design and Verification of Asynchronous FIFO with Novel Architecture Using Verilog HDL

Cited by 9 publications

References 0 publications

Asynchronous FIFO Design Based on Verilog

Asynchronous FIFO Design Based on Verilog

Design and optimization of asynchronous FIFO based on Verilog HDL

High-speed ADC interface design based on JESD204B protocol

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