Design and Verification of Low Voltage Low Power Dynamic Comparator over PVT Variation

Rusli, Julie Roslita; Sidek, Roslina Mohd; Majid, Hasmayadi Abdul; Hassand, W.Z. Wan; Mustafa, Muhammad Norhaffis; Shafie, Suhaidi

doi:10.1109/icsima.2018.8688785

Cited by 2 publications

(1 citation statement)

References 9 publications

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“…Also in the work of Ayesh et al, a single‐ended charge steering dynamic comparator, which offers a kickback noise of 3 mV is described. In other works, other topologies of dynamic comparators are shown exhibiting different performance, although their kickback effect reduction is not quantified.…”

Section: Introductionmentioning

confidence: 96%

A low kickback fully differential dynamic comparator for pipeline analog‐to‐digital converters

Diaz‐Madrid

Doménech‐Asensi

Hauer

et al. 2019

Engineering Reports

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This study presents a fully differential dynamic comparator with low kickback noise, an effect caused by voltage variations in the regeneration nodes of these types of circuit. Given their low power dissipation, dynamic comparators are key circuits in analog‐to‐digital converters (ADCs), especially in pipelined ADCs. The proposed comparator has been simulated and compared with three other comparator topologies. The value of the kickback noise generated by the proposed circuit is lower than that generated by other conventional dynamic comparators over a wide input range, while simultaneously showing a low offset voltage error. The dynamic comparator has been implemented in a low‐resolution ADC with a resolution of 2.5 effective bits, which has been prototyped in a 0.35‐μm CMOS AMS C35B4 process. Its size is 34 μm × 38 μm.

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Section: Introductionmentioning

confidence: 96%

A low kickback fully differential dynamic comparator for pipeline analog‐to‐digital converters

Diaz‐Madrid

Doménech‐Asensi

Hauer

et al. 2019

Engineering Reports

View full text Add to dashboard Cite

show abstract

Review on High-Speed Dynamic Comparators for Analog to Digital Converters

Krishna,

Nambath

2024

J CIRCUIT SYST COMP

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This paper presents a comprehensive review of the state-of-art high-speed dynamic comparators. The comparator is a critical block of high-speed, low-power analog-to-digital converters, determining the speed and overall power consumption. Therefore, the design of a high-speed comparator with tolerable offset, noise and power consumption is of utmost importance. Recent work reported on high-speed comparator topologies is investigated in detail with the help of simulations in 65nm CMOS technology. Various parameters, such as delay, energy consumption, speed, offset, kickback noise, power delay product, etc., are compared. A detailed comparative study is also presented on several design methodologies.

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Design and Verification of Low Voltage Low Power Dynamic Comparator over PVT Variation

Cited by 2 publications

References 9 publications

A low kickback fully differential dynamic comparator for pipeline analog‐to‐digital converters

A low kickback fully differential dynamic comparator for pipeline analog‐to‐digital converters

Review on High-Speed Dynamic Comparators for Analog to Digital Converters

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