Design and Verification of Real-Life Processes With Application of Petri Nets

Grobelna, Iwona; Wiśniewski, Remigiusz; Grobelny, Michał; Wiśniewska, M.

doi:10.1109/tsmc.2016.2531673

Cited by 62 publications

(34 citation statements)

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“…Control processes are already well described in the literature. There are various specification techniques of control processes [ 10 ], including Petri nets (PN) [ 11 , 12 , 13 ], statecharts [ 14 ] and diagrams of the Unified Modelling Language (UML) [ 15 , 16 ]. There are also some approaches to using these specification techniques in the domain of cyber-physical systems, such as [ 17 , 18 , 19 , 20 , 21 , 22 , 23 ].…”

Section: Introductionmentioning

confidence: 99%

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Formal Verification of Control Modules in Cyber-Physical Systems

Grobelna

2020

Sensors

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The paper proposes a novel formal verification method for a state-based control module of a cyber-physical system. The initial specification in the form of user-friendly UML state machine diagrams is written as an abstract rule-based logical model. The logical model is then used both for formal verification using the model checking technique and for prototype implementation in FPGA devices. The model is automatically transformed into a verifiable model in nuXmv format and into synthesizable code in VHDL language, which ensures that the resulting models are consistent with each other. It also allows the early detection of any errors related to the specification. A case study of a manufacturing automation system is presented to illustrate the approach.

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Section: Introductionmentioning

confidence: 99%

“…Each specification technique has its advantages and disadvantages. Petri nets, as a mathematical model, has the wide support of analysis and verification methods [ 12 , 24 , 25 ]. Statecharts [ 14 ] were introduced as a state-based representation of a reactive system.…”

Section: Introductionmentioning

confidence: 99%

Formal Verification of Control Modules in Cyber-Physical Systems

Grobelna

2020

Sensors

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“…clusers, grids, etc. ), (c) computing on GPUs [25,24,20] (d) computing on digital signal processors (DSP) units and (e) computing on FPGA chips [11,15,17,18,27,29]. …”

Section: Introductionmentioning

confidence: 99%

FPGA-based bandwidth selection for kernel density estimation using high level synthesis approach

Gramacki

Sawerwain

Gramacki

2016

Bulletin of the Polish Academy of Sciences Technical Sciences

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Abstract. Field-programmable gate arrays (FPGA) technology can offer significantly higher performance at much lower power consumption than is available from single and multicore CPUs and GPUs (graphics processing unit) in many computational problems. Unfortunately, the pure programming for FPGA using hardware description languages (HDL), like VHDL or Verilog, is a difficult and not-trivial task and is not intuitive for C/C++/Java programmers. To bring the gap between programming effectiveness and difficulty, the high level synthesis (HLS) approach is promoted by main FPGA vendors. Nowadays, time-intensive calculations are mainly performed on GPU/CPU architectures, but can also be successfully performed using HLS approach. In the paper we implement a bandwidth selection algorithm for kernel density estimation (KDE) using HLS and show techniques which were used to optimize the final FPGA implementation. We are also going to show that FPGA speedups, comparing to highly optimized CPU and GPU implementations, are quite substantial. Moreover, power consumption for FPGA devices is usually much less than typical power consumption of the present CPUs and GPUs.Key words: FPGA, high level synthesis, kernel density estimation, bandwidth selection, plug-in selector.FPGA-based bandwidth selection for kernel density estimation using high level synthesis approach In the paper we are concerned with FPGA approach. In [10] the author considers a problem how to use FPGA for fast computing of PDFs using direct very high speed integrated circuits hardware description language (VHDL) programming approach. However, the problem we are concerning is of different nature, as we concentrate our attention for computing the optimal bandwidth for PDF (see Section 2).To develop the final FPGA design we use the high level synthesis (HLS) approach [8,16], in which no direct hardware description language (HDL) coding is needed (typically, VHDL or Verilog languages a are used). The remainder of the paper is organized as follows. In Section 2, we turn our attention to give the reader some preliminary information on KDE and bandwidth selection. In Section 3 we provide detailed mathematical formulas for calculating optimal bandwidth using the PLUGIN method. In Section 4 we cover all the necessary details on our FPGA-based implementation. We also present practical experiments carried out and discuss the results. In Section 5, we conclude the paper. Kernel density estimation and bandwidth selectionThe univariate kernel density estimator fˆ for a random sample X i (i = 1, 2, …, n), drawn from a common and usually unknown density function f is given by a It is worth to note that OpenCL framework, which is commonly used by GPU programmers, also becomes available for FPGA devices. Nowadays, OpenCL is offered by Altera SDK for OpenCL to easily implement OpenCL applications for FPGA. Recently, Xilinx announced a similar solution, namely SDAccel Development Environment for OpenCL, C, and C++.

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“…This is particularly important in concurrent and distributed systems where traditional methods of software testing are not applicable. The formal verifications of such systems is a ground for many current scientific projects [11]. The ongoing research on the Alvis language include also building an Alvis simulator, Alvis Virtual Machine [12] and automatic Java code generation [13].…”

Section: Introductionmentioning

confidence: 99%

Alvis models of safety critical systems state-base verification with nuXmv

Biernacki

2016

Annals of Computer Science and Information Systems

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Abstract-For modelling of real-time safety critical systems, when traditional testing techniques cannot be applied, formal system verification is crucial. Alvis is a modelling language that combines possibilities of formal models verification with flexibility and simplicity of practical programming languages. Solutions introduced in Alvis make the development process easier and help engineers to cope with more complex systems. The paper deals with a state-based approach to the verification of Alvis models. Until the research presented in the paper were conducted, the verification process was mostly action-based. The nuXmv tool, as one of the top model checkers, was selected for the task of state-base verification of Alvis models translated into the SMV modelling language. The paper presents a translation algorithm and usability studies performed on existing safety critical systems.

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Design and Verification of Real-Life Processes With Application of Petri Nets

Cited by 62 publications

References 62 publications

Formal Verification of Control Modules in Cyber-Physical Systems

Formal Verification of Control Modules in Cyber-Physical Systems

FPGA-based bandwidth selection for kernel density estimation using high level synthesis approach

Alvis models of safety critical systems state-base verification with nuXmv

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