Design automation for mask programmable fabrics

Abstract

Programmable circuit design has played an important role in improving design productivity over the last few decades. By imposing structure on the design, efficient automation of synthesis, placement and routing is possible. We focus on a class of programmable circuits known as mask programmable circuits. In this paper, we describe key issues in design and tool methodology that need to be addressed in creating a programmable fabric. We construct an efficient design flow that can explore different logic and routing architectures. The main advantage of our work is that we tailor tools designed for standard cell design, that are readily available in the market, to work on a programmable fabric. Our flow requires some additional software capability. A special router that understands programmable routing constructs to complete connections is described. In addition, a tool that packs logic efficiently after synthesis is also presented.

Standard Cell Like Via-Configurable Logic Blocks for Structured ASIC in an Industrial Design Flow

“…This is a better approach. 2 In fact, two VPEX2 instances alone cannot realize a D flip-flop. However, similar to that proposed in [28], we employ some M3 wires not belonging to VPEX2 instances to realize the D flip-flop in VPEX2L.…”

“…After several years of relentless effort, structured ASIC vendors have developed a variety of products with different technology features. Table I shows the programmability choices and the granularity of CLBs adopted by some vendors [2], [3], [5], [14]- [27] and research groups [1], [7], [28], [29]. This is by no means an exhaustive list.…”

Design and analysis of via-configurable routing fabrics for structured ASICs

“…A more prominent feature of structured ASIC is its layout regularity. A via-configurable structured ASIC consists of via-configurable logic block (VCLB) arrays and routing fabric block arrays [4][5][6][7][8]. Its layout regularity will not only simplify the set of restricted design rules [9], but also greatly enhance the effects of various reticle enhancement techniques for improving manufacturability [10][11][12][13].…”

“…A structured ASIC router customizes a few via layers on a predefined routing fabric to implement connections among logic blocks. In the past, a few structured ASIC routers [7,14,15] were designed only for evaluating a structured ASIC technology. A more comprehensive structured ASIC router was presented in [16].…”

Clock routing for structured ASICs with via-configurable fabrics

“…With regard to this aspect, a design style for structured ASIC should leverage most of existing tools either for standard cell or FPGA designs. The works in [5,6,9,12] purport a standard-cell like structured ASIC design style. To enable such a design style, VCLBs [9,10,12] forming logic fabrics should be designed to facilitate the use of standard cell synthesis and analysis tools.…”