Design centering/yield optimization of power aware band pass filter based on CMOS current controlled current conveyor (CCCII+)

Yield-driven power-delay-optimal CMOS full-adder design complying with automotive product specifications of PVT variations and NBTI degradations

“…To save the amount of the numerical simulation cost, it is reasonable to first optimize the circuit safety margin without including the process variations [23,33]. Thus, the optimization task has been divided into a nominal optimization phase and a subsequent yield optimization assuming process variations.…”

“…In [23][24][25], the authors reported SQP/least square and WCD algorithm-based interactive circuit sizing and yield optimization for analog and digital circuits considering statistical variations in a defined range of operating conditions.…”

Optimal transistor sizing for maximum yield in variation‐aware standard cell design

“…This paper presents the application of mathematical optimization to the design of standard cells that are robust to process variations even in worst-case operating conditions. In order to achieve effective variation-aware design, we must thoughtfully account both the statistical inter-die and intra-die variations, and the operating condition fluctuations.As a result, statistical optimization for yield has become a crucial task in IC design, and because the specifications of an IC usually have challenging trade-offs, requiring multidimensional, multiobjective optimization, the role of mathematical techniques for circuit analysis and yield optimization has become essential to obtain solutions that satisfy the requested performance in the least time effort [6][7][8][9]14]. The approach is demonstrated for a 40 nm low-power standard threshold voltage Complementary Metal Oxide Semiconductor (CMOS) technology, for an intended operating temperature range [À40°C, 125°C] and supply voltage range [0.95 V, 1.05 V].…”

“…Such characteristics limit the accuracy of the digital corners and cannot be considered as accurate indicators of performance variation bounds [25]. In order to achieve effective variation-aware design, we must thoughtfully account both the statistical inter-die and intra-die variations, and the operating condition fluctuations.As a result, statistical optimization for yield has become a crucial task in IC design, and because the specifications of an IC usually have challenging trade-offs, requiring multidimensional, multiobjective optimization, the role of mathematical techniques for circuit analysis and yield optimization has become essential to obtain solutions that satisfy the requested performance in the least time effort [6][7][8][9]14]. Transistor level designs like standard cells are most susceptible to parametric yield issues caused by process/operating variations [10,11,13,16,17,23] and are the scope of this work.…”