Design challenges of a 65 nm CMOS stacked folded differential PA structure for mobile communications

Abstract

This paper presents a 65 nm CMOS-Power Amplifier (PA) designed for mobile communications. The PA is based on a new structure, the Stacked Folded Differential Structure (SFDS) which is inspired from a push-pull structure. The PA is designed for the UMTS W-CDMA standard which requires linearity from -20 to 24 dBm output power. The PA provides 27 dBm maximal output power (P max ) with 15% of power added efficiency (PAE) at 1.8 GHz under 2.2 V supply. The linear gain is 13 dB and the compression point (OCP 1 ) is 25.5 dBm. With a HPSK modulation, the adjacent channel leakage ratio (ACLR) is respected until 23 dBm with -34.17 and -33.70 dBc at -5 and ?5 MHz respectively. The PA die area is 0.65 mm 2 .