Design considerations for CMOS digital circuits with improved hot-carrier reliability

Test-wrapper designs for the detection of signal-integrity faults on core-external interconnects of SoCs

“…Repeated overshoots, however, are known to be able to cause hot-carrier damage in MOS transistors [12]. These hot-carriers might penetrate the gate oxide, leading to permanent changes in the oxide charge distribution, and creating serious reliability concerns for the circuit over time [7,13]. It is therefore important to detect the occurrences of overshoots in all possible situations as part of the manufacturing test flow.…”

“…While overshoots lead to functional errors if only if they occur during latching windows, their adverse impact on chip reliability is a major concern [13]. In this paper, at the interconnect receiving side, we also design a new overshoot detector, which, compared to the one introduced in [20], is able to detect overshoots in all possible situations.…”

Fast postplacement optimization using functional symmetries

“…For example, input slew rate to a transistor and effective output switching are identified as the most important factors [12], [15] determining device degradation. Due to the resistive behavior of deep submicron interconnects, estimation of slew rates at the gate level is very inaccurate when the placement and routing information is unknown.…”

Signal Integrity: Fault Modeling and Testing in High-Speed SoCs

“…The most important ones are: crosstalk (signal distortion due to cross coupling effects between signals) [1] [2], overshoot (signal rising momentarily above the power supply voltage) [3] [4], reflection (echoing back a portion of a signal), electro-magnetic interference (resulting from the antenna properties) [5], power supply noise [6] and signal skew (delay in arrival time to different receivers) [7] [8].…”