Design Considerations for the Development of Computational Resistive Memories

Pinto, Felipe Chiarello de Souza; Vourkas, Ioannis

doi:10.1109/lascas51355.2021.9459165

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Cited by 2 publications

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Memristive Based In-Memory Computing Using Novel RISC-V Architectures

Mallios,

Tompris,

Passias

et al. 2024

2024 Panhellenic Conference on Electronics &Amp;amp; Telecommunications (PACET)

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Memristive Based In-Memory Computing Using Novel RISC-V Architectures

Mallios,

Tompris,

Passias

et al. 2024

2024 Panhellenic Conference on Electronics &Amp;amp; Telecommunications (PACET)

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Robust Circuit and System Design for General-Purpose Computational Resistive Memories

Pinto¹,

Vourkas²

2021

Electronics

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Resistive switching devices (memristors) constitute a promising device technology that has emerged for the development of future energy-efficient general-purpose computational memories. Research has been done both at device and circuit level for the realization of primitive logic operations with memristors. Likewise, important efforts are placed on the development of logic synthesis algorithms for resistive RAM (ReRAM)-based computing. However, system-level design of computational memories has not been given significant consideration, and developing arithmetic logic unit (ALU) functionality entirely using ReRAM-based word-wise arithmetic operations remains a challenging task. In this context, we present our results in circuit- and system-level design, towards implementing a ReRAM-based general-purpose computational memory with ALU functionality. We built upon the 1T1R crossbar topology and adopted a logic design style in which all computations are equivalent to modified memory read operations for higher reliability, performed either in a word-wise or bit-wise manner, owing to an enhanced peripheral circuitry. Moreover, we present the concept of a segmented ReRAM architecture with functional and topological features that benefit flexibility of data movement and improve latency of multi-level (sequential) in-memory computations. Robust system functionality is validated via LTspice circuit simulations for an n-bit word-wise binary adder, showing promising performance features compared to other state-of-the-art implementations.

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Design Considerations for the Development of Computational Resistive Memories

Cited by 2 publications

References 13 publications

Memristive Based In-Memory Computing Using Novel RISC-V Architectures

Memristive Based In-Memory Computing Using Novel RISC-V Architectures

Robust Circuit and System Design for General-Purpose Computational Resistive Memories

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