Design considerations in scaled SONOS nonvolatile memory devices

Bu, Jianhui; White, M.H.

doi:10.1016/s0038-1101(00)00232-x

Cited by 151 publications

(77 citation statements)

References 29 publications

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“…However, floating-gate based flash memory has been reported to have limits in continuous device scaling due to increasing cell-to-cell interference, decreasing coupling ratio, non-scalable tunnelling oxide thickness, decreasing tolerance for charge loss, etc. Therefore, active research has been performed on flash memory devices with discrete charge trapping layers, such as silicon-oxide-nitride-oxide-silicon (SONOS) devices [29][30][31][32][33]25] or nanocrystal (NC)-based memory devices (nano-floating gate memory devices) [34][35][36][37][38]. Because of their better endurance, smaller chip size, and lower power consumption when compared with floating-gate devices, this technology is of great interest to the electronics industry.…”

Section: Introductionmentioning

confidence: 99%

Recent progress in gold nanoparticle-based non-volatile memory devices

Jang‐Sik

2010

Gold Bull

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Recently, much progress has been made toward the fabrication of non-volatile memory devices based on metallic nanoparticles. Among the many kinds of nanoparticles, gold nanoparticles are some of the most widely used materials for charge trapping elements in non-volatile memory devices because they are chemically stable, easily synthesized, and have a high work function. Various synthesis methods have been applied to fabricate gold nanoparticle-based nonvolatile memory devices and recent progress indicates that gold is a very promising material for non-volatile memory applications. In this article, the recent advances in fabrication and characterization of gold nanoparticle-based nonvolatile memory devices, with an emphasis on flash memory-type memory devices, are reviewed. Detailed device fabrication, characterization, and future directions are reported based on the recent research activities and literature.

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Section: Introductionmentioning

confidence: 99%

Recent progress in gold nanoparticle-based non-volatile memory devices

Jang‐Sik

2010

Gold Bull

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“…Zhu et al 2 indicated that the trapped charges located in both interface and bulk in the HfO 2 layer. Bu and White 3 found that the charges concentrated on the interface between the block and trap layer, whereas Zahid et al 4 reported that electrons aggregated in the interface between the metal gate and block Al 2 O 3 layer and those electrons could vary the threshold voltage, which was confirmed by Rao et al 5 and Padovani et al 6 Sharma et al 7 showed that the holes generated in the SiO x N y trap layer might cause the profiled electron centroid moving towards the HfO 2 block layer. Ko et al 8 pointed that oxygen interstitials or Hf vacancies, beside the oxygen vacancies, may have the important roles as the charged point defects in charge-trapping process.…”

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confidence: 99%

In situ electron holography study of charge distribution in high-κ charge-trapping memory

Yao

Huo

et al. 2013

Nat Commun

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Charge-trapping memory with high-k insulator films is a candidate for future memory devices. Many efforts with different indirect methods have been made to confirm the trapping position of the charges, but the reported results in the literatures are contrary, from the bottom to the top of the trapping layers. Here we characterize the local charge distribution in the high-k dielectric stacks under different bias with in situ electron holography. The retrieved phase change induced by external bias strength is visualized with high spatial resolution and the negative charges aggregated on the interface between Al 2 O 3 block layer and HfO 2 trapping layer are confirmed. Moreover, the positive charges are discovered near the interface between HfO 2 and SiO 2 films, which may have an impact on the performance of the chargetrapping memory but were neglected in previous models and theory.

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“…The electric field across the tunnel oxide is calculated using Physics Based TCAD simulations. 3,4,21 With 1 V gate voltage; the electric field across the tunnel oxide is 0.36 MV/cm, and with a 10 V gate voltage; the electric field is 3.6 MV/cm. At an electric field of 1 MV/cm; tunneling over a potential barrier of 1.36 eV is negligible.…”

Section: à2mentioning

confidence: 99%