Design diversity redundancy with spatial-temporal voting applied to data acquisition systems

Chenet, Cristiano P.; Lanot, Alisson J. C.; Balen, Tiago R.

doi:10.1109/latw.2014.6841900

Cited by 4 publications

(3 citation statements)

References 23 publications

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“…Additionally, the application is a fault tolerant mixed-signal system based on design diversity, comprising three ADCs, besides digital hardware and software resources for controlling the converters and the direct memory access, as well as to perform the voting. Therefore, experimental results also allows to validate the previously proposed mitigation technique [12].…”

Section: Introductionmentioning

confidence: 78%

“…Design diversity can enhance the system reliability to common-mode faults because each module may have different levels of resilience, therefore the probability of multiple domain faults may be reduced. The main objective of this technique is to avoid multiple errors that may arise due to commonalities among the system copies, by using different hardware devices, different clock frequencies, and different software implementations [12].…”

Section: B Fault Tolerance With Design Diversitymentioning

confidence: 99%

“…In previous works of our research group [4], [12], we proposed the application of a mitigation strategy based on modular redundancy with design diversity to a data acquisition system, prototyped in a PSoC (Programmable System-on-Chip) device. In the mentioned works, a compiled-time fault injection was carried out, by manually inserting bit-flips in few registers of the architecture, since the purpose was only to validate the spatial-temporal voting scheme proposed in those works.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Fault Injection on a Mixed-Signal Programmable SoC with Design Diversity Mitigation

Aguilera¹,

Chenet²,

Balen³

2020

JICS

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This paper presents an approach for runtime software-based fault injection, applied to a commercial mixed-signal programmable system-on-chip (PSoC). The fault-injection scheme is based on a pseudo-random sequence generator and software interruption. A fault tolerant data acquisition system, based on a design diversity redundant scheme, is considered as case study. The fault injection is performed by intensively inserting bit flips in the peripherals control registers of the mixed-signal PSoC blocks, as well as in the SRAM memory of the device. Results allow to evaluate the applied fault tolerance technique, indicating that the system is able to tolerate most of the generated errors. Additionally, a high fault masking effect is observed, and different criticality levels are observed for faults injected into the SRAM memory and in the peripherals control registers.

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Section: Introductionmentioning

confidence: 78%

Section: B Fault Tolerance With Design Diversitymentioning

confidence: 99%