Design-Efficient Approximate Multiplication Circuits Through Partial Product Perforation

Zervakis, Georgios; Tsoumanis, Kostas; Xydis, Sotirios; Soudris, Dimitrios; Pekmestzi, Kiamal

doi:10.1109/tvlsi.2016.2535398

Cited by 117 publications

(85 citation statements)

References 27 publications

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“…Approximations can be applied to any digital circuit in various ways like probabilistic pruning and inexact logic minimization, where the authors of [12] used the latter technique in data path elements. When approximations are implemented in any architecture, the difference in output bits of exact and approximate circuits can be calculated using the equations given in [13][14]. Peter.A et.al of [15] has given approaches and challenges of ML in design automation i.e ML applications to VLSI designs.…”

Section: Related Workmentioning

confidence: 99%

Supervised Machine Learning for Training a Neural Network as 5:2 Compressor

Maddisetti¹,

Senapati²,

JVR³

2019

IJITEE

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Machine Learning has achieved substantial development in numerous applications like image processing, pattern recognition, approximate computing etc. This paper interlinks supervised machine learning algorithm and VLSI architectures to train a neural network as exact and approximate 5:2 compressors. Probabilistic pruning type of approximation technique has been employed on the exact 5:2 compressor. This approximation technique on compressors reduces the power consumption with variation in the outputs without affecting the error limit. The simulation of 5:2 compressors and training of neural network using machine learning algorithm has been done using Spectre simulator of Cadence Design Systems at 45nm CMOS technology node and Keras library with TensorFlow background respectively.

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Section: Related Workmentioning

confidence: 99%

Supervised Machine Learning for Training a Neural Network as 5:2 Compressor

Maddisetti¹,

Senapati²,

JVR³

2019

IJITEE

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“…Zervakis et al 25 proposed a partial product perforation method which aimed to reduce the number of partial products that were accumulated for completing the multiplication process. The proposed method was said to decrease the area, power, and depth of the accumulation tree.…”

Section: Related Workmentioning

confidence: 99%

“…Many researches focus on improving upon this design. 20,21,[25][26][27][28] The authors in Abed et al 20 proposed a hybrid Wallace tree algorithm to tackle the lengthy interconnects in Wallace tree multipliers and reduce the power dissipation and the gate usage using counters. The main differences between the conventional and the algorithm proposed in Abed et al 20 are as follows: (7, 3) and (2, 3, 3) counters were used in addition to the full and half adders, and CLA is used for final bit additions.…”

Section: Conventional and Hybrid Wallace Tree Multipliermentioning

confidence: 99%

High‐performance low‐power approximate Wallace tree multiplier

Abed

Khalil

Modhaffar

et al. 2018

Circuit Theory & Apps

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Multipliers are considered critical functional units in many systems like DigitalSignal Processing (DSP), machine learning, and so on. The overall performance of such systems are dependent on the efficiency of multipliers. However, multipliers are slow and power inefficient components due to their complex circuits, so we aim to reduce their power consumption by relaxing their accuracy requirements and at the same time enhancing their speed. In this paper, we present a fast and a power-aware multiplier that targets error-resilient systems. This is achieved by using our proposed approximation algorithm, a hybrid Wallace tree technique for reducing power consumption, and a hybrid ripple-carry adder for reducing latency. The proposed approximation algorithm is implemented using both a modified bit-width aware and carry-in prediction technique, while the proposed hybrid Wallace tree is implemented using high order counters. These proposed algorithms are implemented using HDL language, synthesized, and simulated using Quartus and Modelsim tools. For a 16-bit multiplier, a mean accuracy of 98.35% to 99.95% was achieved with a 45.77% reduction in power, a 21.48% drop in latency, and a 34.95% reduction in area. In addition, our design performs even better for larger size multipliers (32bit multiplier) where a 61.24% reduction in power was achieved, with an 8.74%drop in latency and a 35.24% reduction in area with almost no loss in accuracy. /journal/cta to overcome common performance metrics such as area, speed, and/or power consumption. Booth algorithm, 1 Wallace tree, 2,3 Dadda tree, 4 and array multiplier 5 are examples of such designs. Wallace tree multiplier is one of the best parallel designs used to reduce the multiplier's latency by adding partial products in parallel.Applications including multimedia, 6 neural networks, 7 DSP filtering, 8 and machine learning are error tolerant and do not require a perfect accuracy in computation; hence, getting an approximate result is sufficient. In multimedia applications, as an example, getting precise results is not always required because human observation is limited. For such applications, implementations can be relaxed in order to reduce power consumption, accelerate computations, and minimize area, thus, achieving better performance. Approximate computing is an emerging computing paradigm to enhance the performance of error-tolerant applications. 9-11 According to Han and Orshansky, 10 applications suitable for approximate computing can be classified into four classes: applications with analog inputs, applications with analog outputs, applications with no unique answers, and lastly iterative and convergent applications.Adders and multipliers are the two main components used for approximations. Many research works have been conducted on approximate implementations that are based on adders and can be found in Gupta et al, Zhu et al, On the other hand, fewer works exist in the field of approximate multipliers. Some algorithms used for approximate multipliers are truncation, ...

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“…While, the performance of different kinds of computing methods such as Wallace, Dadda, Compr. 4:2 have been compared in an accurate and approximate manner [7]. Then, a new approximate Wallace tree multiplier (AWTM) has been presented, which obtained a mean accuracy of 99.85% to 99.965% [8].…”

Section: Introductionmentioning

confidence: 99%