Design Exploration and Code Optimizations for FPGA-Based Post-Quantum Cryptography using High-Level Synthesis

Guerrieri, Andrea L.; Marques, Gabriel Da Silva; Regazzoni, Francesco; Upegui, Andrés

doi:10.36227/techrxiv.19404413.v1

Cited by 1 publication

(1 citation statement)

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“…HLS has been extensively used to deliver hardware implementations of the candidates of the NIST PQC contest, including lattice-based KEMs [1], the Classic McEliece code-based KEM [4], and comprehensive implementations of both latticebased KEM and digital signature schemes [5]. A HW/SW codesign approach exploiting HLS to design hardware accelerators was successfully employed targeting Classic McEliece [4] and lattice-based cryptosystems [6].…”

Section: Introduction and Related Workmentioning

confidence: 99%

Hardware-Software Co-Design of BIKE with HLS-Generated Accelerators

Montanaro

Galimberti

Colizzi

et al. 2022

2022 29th IEEE International Conference on Electronics, Circuits and Systems (ICECS)

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In order to mitigate the security threat of quantum computers, NIST is undertaking a process to standardize postquantum cryptosystems, aiming to assess their security and speed up their adoption in production scenarios. Several hardware and software implementations have been proposed for each candidate, while only a few target heterogeneous platforms featuring CPUs and FPGAs. This work presents a HW/SW co-design of BIKE for embedded platforms featuring both CPUs and small FPGAs and employs high-level synthesis (HLS) to timely deliver the hardware accelerators. In contrast to state-of-the-art solutions targeting performance-optimized HLS accelerators, the proposed solution targets the small FPGAs implemented in the heterogeneous platforms for embedded systems. Compared to the softwareonly execution of BIKE, the experimental results collected on the systems-on-chip of the entire Xilinx Zynq-7000 family highlight a performance speedup ranging from 1.37×, on Z-7010, to 2.78×, on Z-7020.

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