Design, Fabrication, and Characterization of Ultrathin 3-D Glass Interposers With Through-Package-Vias at Same Pitch as TSVs in Silicon

Micro/Nano-scale integrated circuits and new emerging hybrid integration techniques

“…传统的柔性聚合物转接板, 其热膨胀系数与 IC 不匹配, 尺寸稳定性较差; 传统的硅基转接板, 进 行 TSV 正面工艺时, 需要进行绝缘层淀积, 进行背面工艺时, 需要进行 TSV 绝缘开口制作, 绝缘层的 质量对转接板性能影响很大, 制作成本高; 而玻璃转接板, 因其良好的绝缘性能、尺寸稳定性、热膨胀 系数与 IC 兼容等优点 [132,133] , 逐渐成为研究热点. 美国佐治亚理工学院的封装研究中心 (PRC) 在 2014 年报道了双面金属化的超薄玻璃转接板的 制作与测试分析, 玻璃转接板厚度只有 30 µm, 玻璃通孔 (through glass via, TGV) 直径 15∼40 µm, 基本上达到了硅转接板的线条精度 [134] . TGV 通过 193 nm 准分子激光器刻蚀而成, 电镀铜填充, 转 接板上下表面各有一层 Cu 互连, 线宽只有 4 µm.…”

Low-Loss, High-Linearity RF Interposers Enabled by Through Glass Vias

“…Glass has excellent RF properties including a very high resistivity, low dielectric constant and a low loss tangent [5]. Moreover, glass offers panel-based manufacturability utilizing large panel sizes which reduces the overall cost [6]. Finally, the CTE of glass can be adjusted to achieve thermal compatibility with ICs as well as printed circuit boards which manages the warp for IC stacking [6].…”

“…TGVs based on localized glass reflow in silicon have been shown to achieve excellent RF performance but at the expense of fabrication complexity, time and cost [5]. Similarly, ultra-thin 3-D glass interposers with TGVs using panel-based fabrication process have achieved good RF results but require additional fabrication steps [6]. Recently, Corning Inc. has shown a TGV technology with high thermal reliability but require chemical mechanical polishing (CMP) and specialized thin wafer handling [7].…”

Effect of Wafer Level Underfill on the Microbump Reliability of Ultrathin-Chip Stacking Type 3D-IC Assembly during Thermal Cycling Tests

“…Given that chip-stacking packages, combined with either silicon-based or glass/ceramic-based interposers, are promising frameworks [ 1 , 2 , 3 , 4 , 5 ] for three-dimensional integrated circuit (3D-IC) integrations [ 6 , 7 , 8 ], microbump (μ-bump) reliability must be enhanced. Processes, such as chip grinding, position adjustment and planarity of assembly, the formation of through-silicon via (TSV), and the composition and dimensions of μ-bumps, should be emphasized to improve the functionality of 3D-IC packages.…”