Design for 3D Integration and Applications

Franzon, Paul D.; Davis, W. Rhett; Steer, M.B.; Hao, Hua; Lipa, S.; Luniya, Sonali R.; Mineo, C.; Oh, Julie; Sule, Ambarish Mukund; Thorolfsson, Thorlindur

doi:10.1109/issse.2007.4294463

Cited by 10 publications

(7 citation statements)

References 11 publications

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“…This assumption of homogeneous 3D ICs is reasonable since stacking identical layers can reduce both design efforts and manufacturing costs [19]. The 3D many-core processor has either 128 cores or 256 cores.…”

Section: D Many-core Processor Architecturementioning

confidence: 99%

New Thermal-Aware Voltage Island Formation for 3D Many-Core Processors

Hong¹,

Lim²,

Lim³

et al. 2015

ETRI J

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The power consumption of 3D many-core processors can be reduced, and the power delivery of such processors can be improved by introducing voltage island (VI) design using on-chip voltage regulators. With the dramatic growth in the number of cores that are integrated in a processor, however, it is infeasible to adopt per-core VI design. We propose a 3D many-core processor architecture that consists of multiple voltage clusters, where each has a set of cores that share an on-chip voltage regulator. Based on the architecture, the steady state temperature is analyzed so that the thermal characteristic of each voltage cluster is known. In the voltage scaling and task scheduling stages, the thermal characteristics and communication between cores is considered. The consideration of the thermal characteristics enables the proposed VI formation to reduce the total energy consumption, peak temperature, and temperature gradients in 3D many-core processors.Keywords: Many core, task scheduling, thermal aware, three-dimensional integration, voltage island. Manuscript received Mar. 1, 2014; revised Sept. 17, 2014; accepted Oct. 6, 2014 I. IntroductionThe use of multiple supply voltages through the design of voltage islands (VIs) has been introduced into system-on-chip (SoC) design to minimize power consumption levels. A VI in a many-core processor is a set of cores that are physically contiguous and are powered by the same supply voltage. Timing-critical tasks are assigned to the cores in the VI that are powered by higher supply voltages so that the performance constraint can be met. Meanwhile, tasks that are not timingcritical are assigned to the cores in the VI that are powered by lower supply voltages; thus, these cores run more slowly, thereby reducing the total power consumption [1]- [2].Three-dimensional (3D) integration technology has been accepted as a solution to the problems faced by traditional twodimensional (2D) integration technology. In 3D ICs, the global wire length is reduced by a factor of √k, where k is the number of stacked layers [3]. Recently, microprocessor design has been shifting from multi-core to many-core configurations due to the power wall that multi-core processors are facing [4]. The performance of many-core processors can be improved using 3D integration technology because the on-chip communications are significantly shortened. Integrated multiple core dies are accepted as a promising alternative to be used in future high-performance computing systems [5].Although 3D stacking of core layers offers a lot of advantages, some existing problems may be exacerbated. One of the challenges is the thermal crisis. The power density per unit volume considerably increases compared to 2D technology, so the peak temperature may soar. It was shown that the peak temperature of a 3D chip made of two layers increased by more than 20°C without any modifications to mitigate the thermal problems [6]. The temporal and spatial temperature gradients also become larger due to the thermal characteristics of stacked lay...

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Section: D Many-core Processor Architecturementioning

confidence: 99%

New Thermal-Aware Voltage Island Formation for 3D Many-Core Processors

Hong¹,

Lim²,

Lim³

et al. 2015

ETRI J

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“…This assumption of homogeneous 3D ICs is reasonable since stacking identical layers can reduce both design efforts and manufacturing costs [2]. Eight cores are on a die and the die count varies from two to four.…”

Section: D Multicore Architecture and Thermal Characteristicsmentioning

confidence: 99%

Dynamic thermal management for 3D multicore processors under process variations

Hong

Lim

et al. 2013

IEICE Electron. Express

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Stacking core layers is emerging as an alternative for future high performance computing, but thermal problems have to be tackled first. When adaptive voltage scaling is adopted to hide the growing variation in the performance of cores, as a result, heat generation of each core varies. By exploiting the static thermal characteristics, the efficiency of dynamic thermal management can be improved. The proposed thermal management reduces the energy consumption by up to 30.02% compared with existing techniques, while keeping the ratio of temperature violations around 1%.

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“…Since interconnect wires with their supporting repeaters consume a significant portion of total active power, the average interconnect length reduction in 3D IC will significantly reduce overall power consumption [7].…”

Section: Enhancing Performance and Form Factormentioning

confidence: 99%

A Stackable LTE Chip for Cost-effective 3D Systems

Lafi

Lattard

Jerraya

2012

IPSJ Transactions on System LSI Design Methodology

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Abstract:To address the problem of prohibitive cost of advanced fabrication technologies, one solution consists in reusing masks to address a wide range of ICs. This could be achieved by a modular circuit that can be stacked to build TSV-based 3D systems with processing performance adapted to several applications. This paper focuses on 4G wireless telecom applications. We propose a basic circuit that meets the SISO (Single Input Single Output) transmission mode. By stacking multiple instances of this same circuit, it will be possible to address several MIMO (Multiple Input Multiple Output) modes. The proposed circuit is composed of several processing units interconnected by a 3D NoC and controlled by a host processor. Compared to a 2D reference platform, the proposed circuit keeps at least the same performance and power consumption in the context of 4G telecom applications, while reducing total cost. More generally, our cost analysis shows that 3D integration efficiency depends on the size of the circuit and the stacking option (die-to-die, die-to-wafer and interposer-based stacking).

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Design for 3D Integration and Applications

Abstract: 3D stacking and integration can provide system advantages equivalent to up to two technology nodes of scaling. This paper explores application drivers and computer aided design (CAD) for 3D ICs.

Cited by 10 publications

References 11 publications

New Thermal-Aware Voltage Island Formation for 3D Many-Core Processors

New Thermal-Aware Voltage Island Formation for 3D Many-Core Processors

Dynamic thermal management for 3D multicore processors under process variations

A Stackable LTE Chip for Cost-effective 3D Systems

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