Design for consecutive transparency method of RTL circuits

Abstract

SUMMARYIn this paper, the authors propose a design for a consecutive transparency method for modifying the design of cores embedded in a system-on-a-chip (SoC), where the cores are register transfer level (RTL) circuits, so that the circuits satisfy consecutive transparency requirements. Consecutive transparency of a core is a property that enables an arbitrary length sequence that is input from each input port to be propagated to the output side in consecutive clock cycles without changing the sequence values or an arbitrary length sequence that is output from each output port to be propagated from the input side in consecutive clock cycles by selecting a configuration (test mode). Therefore, when a consecutively transparent core is embedded in an SoC, that core can be used as a path for consecutive test access to other cores and interconnects within the SoC. For a consecutive test accessible SoC, even when arbitrary test sequences for arbitrary fault models are applied to cores and interconnects, assumed faults must be completely tested by using those sequences. The authors also show through experiments that the area overhead due to the proposed design for consecutive transparency method is lower than when consecutive transparency was implemented according to a bypass path from input to output by using only a multiplexer.