Design for Delay Measurement Aimed at Detecting Small Delay Defects on Global Routing Resources in FPGA

Abstract

SUMMARYSmall delay defects can cause serious issues such as very short lifetime in the recent VLSI devices. Delay measurement is useful to detect small delay defects in manufacturing testing. This paper presents a design for delay measurement to detect small delay defects on global routing resources, such as double, hex and long lines, in a Xilinx Virtex 4 based FPGA. This paper also shows a measurement method using the proposed design. The proposed measurement method is based on an existing one for SoC using delay value measurement circuit (DVMC). The proposed measurement modifies the construction of configurable logic blocks (CLBs) and utilizes an on-chip DVMC newly added. The number of configurations required by the proposed measurement is 60, which is comparable to that required by stuck-at fault testing for global routing resources in FPGAs. The area overhead is low for general FPGAs, in which the area of routing resources is much larger than that of the other elements such as CLBs. The area of every modified CLB is 7% larger than an original CLB, and the area of the on-chip DVMC is 22% as large as that of an original CLB.

An Enhanced Deep Reinforcement Learning-Based Global Router for VLSI Design

“…The neural network in the DQN algorithm is called the Q-network, and DQN uses two Q-networks: they are the predictive Q-network and the target Q-network. The predictive Q-network is used to predict the action-value corresponding to the current state and choose 3 Wireless Communications and Mobile Computing action according to the ε-greedy policy, as shown in Formula (5). The target Q-network is used to calculate the target Q-value using a delayed update method.…”

“…The VLSI routing phase is divided into global routing [3] and detailed routing [4]. The routing area of global routing is divided into uniformly sized grids, and the connections between pins are abstracted as intergrid connections [5]. This phase requires a reasonable allocation of wires to the grids and guides detailed routing.…”