Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs

Abstract

As integrated circuits (ICs) continue to scale to smaller dimensions, long interconnects have become the dominant contributor to circuit delay and a significant component of power consumption. In order to reduce the length of these interconnects, 3D integration and 3D stacked ICs (3D SICs) are active areas of research in both academia and industry. 3DSICs not only have the potential to reduce average interconnect length and alleviate many of the problems caused by long global interconnects, but they can offer greater design flexibility over 2D ICs, significant reductions in power consumption and footprint in an era of mobile applications, increased on-chip data bandwidth through delay reduction, and improved heterogeneous integration.Compared to 2D ICs, the manufacture and test of 3D ICs is significantly more complex.Through-silicon vias (TSVs), which constitute the dense vertical interconnects in a die stack, are a source of additional and unique defects not seen before in ICs. At the same time, testing these TSVs, especially before die stacking, is recognized as a major challenge.The testing of a 3D stack is constrained by limited test access, test pin availability, power, and thermal constraints. Therefore, efficient and optimized test architectures are needed to ensure that pre-bond, partial, and complete stack testing are not prohibitively expensive.Methods of testing TSVs prior to bonding continue to be a difficult problem due to test access and testability issues. Although some built-in self-test (BIST) techniques have been proposed, these techniques have numerous drawbacks that render them impractical. In this dissertation, a low-cost test architecture is introduced to enable pre-bond TSV test through iv TSV probing. This has the benefit of not needing large analog test components on the die, which is a significant drawback of many BIST architectures. Coupled with an optimization method described in this dissertation to create parallel test groups for TSVs, test time for pre-bond TSV tests can be significantly reduced. The pre-bond probing methodology is expanded upon to allow for pre-bond scan test as well, to enable both pre-bond TSV and structural test to bring pre-bond known-good-die (KGD) test under a single test paradigm.The addition of boundary registers on functional TSV paths required for pre-bond probing results in an increase in delay on inter-die functional paths. This cost of test architecture insertion can be a significant drawback, especially considering that one benefit of 3D integration is that critical paths can be partitioned between dies to reduce their delay. This dissertation derives a retiming flow that is used to recover the additional delay added to TSV paths by test cell insertion.Reducing the cost of test for 3D-SICs is crucial considering that more tests are necessary during 3D-SIC manufacturing. To reduce test cost, the test architecture and test scheduling for the stack must be optimized to reduce test time across all necessary test insertions. This dissertation exam...

An optimal probing method of pre-bond TSV fault identification in 3D stacked ICs

“…Moreover, the BIST circuits themselves are prone to the effects of process variations. References [7] and [8] propose the use of a large probe needle with active driver to short many TSVs together and conduct a parametric test. The set of TSVs contacted at once by the probe needle is referred to as a TSV network.…”

“…High measurement resolution, low hardware overhead and robustness to process variations make this technique likely to be used in practice. Figure 1 shows a circuit model of the test set up [7], [8] for a 4-TSV network. TSV i is represented by its resistance R i and capacitance C i .…”

“…R c represents the contact resistance between TSV and the probe. A gated scan flip-flop (GSF) is inserted between TSV i and the system logic which is in accordance with the developing IEEE P1838 standard [5], [8]. All GSFs can be loaded up or read out through a boundary scan mechanism.…”

“…Now, C charge is charged faster and the measurement terminates quicker. However, the number of TSVs tested in parallel cannot exceed a constant "r" due to minimum measurement resolution constraint [7], [8]. This resolution of measurement refers to the minimum change in TSV resistance that can be detected by the technique and it is adversely affected by the number of TSVs tested in parallel.…”

“…Networks in a group are tested simultaneously by a probe head containing a large number of needles, each making contact with a single network. Once all contacted networks are tested, the probe head is lifted and repositioned to test the remaining group [7], [8].…”