2011
DOI: 10.3844/jcssp.2011.1252.1260
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Design For Test Technique for Leakage Power Reduction in Nanoscale Static Random Access Memory

Abstract: Problem statement: As technology scales down, the integration density of transistors increases and most of the power is dissipated as leakage. Leakage power reduction is achieved in Static Random Access Memory (SRAM) cells by increasing the source voltage (source biasing) of the SRAM array. Another promising issue in nanoscaled devices is the process parameter variations. Due to these variations, higher source voltage causes the data stored in the cells of the SRAM array to flip (weak cell) in the standby mode… Show more

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Cited by 1 publication
(1 citation statement)
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“…Hamidreza and Lombardi (2007) deal with CNT defects and Defect analysis and single stuck at fault and bridging fault identification in CNTFET. Sivamangai and Gunavathi (2011) proposed a new technique to detect the faulty memory cells which reduces the number of March tests and reduces the time. Kotakoski et al (2007) deals with basic effects of ion irrardiation on carbon nano tubes.…”
Section: Previous Workmentioning
confidence: 99%
“…Hamidreza and Lombardi (2007) deal with CNT defects and Defect analysis and single stuck at fault and bridging fault identification in CNTFET. Sivamangai and Gunavathi (2011) proposed a new technique to detect the faulty memory cells which reduces the number of March tests and reduces the time. Kotakoski et al (2007) deals with basic effects of ion irrardiation on carbon nano tubes.…”
Section: Previous Workmentioning
confidence: 99%