2006
DOI: 10.1109/ats.2006.260958
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Design for Testability of Software-Based Self-Test for Processors

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Cited by 19 publications
(2 citation statements)
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“…Functional test sequences can also be generated on chip by using a built-in test generation method [Chen and Dey 2001;Parvathala et al 2002;Kranitis et al 2005;Nakazato et al 2006]. However, sequential test generation provides a higher gate-level fault coverage by targeting gate-level faults directly.…”
Section: Introductionmentioning
confidence: 99%
“…Functional test sequences can also be generated on chip by using a built-in test generation method [Chen and Dey 2001;Parvathala et al 2002;Kranitis et al 2005;Nakazato et al 2006]. However, sequential test generation provides a higher gate-level fault coverage by targeting gate-level faults directly.…”
Section: Introductionmentioning
confidence: 99%
“…In addition, they avoid overtesting of delay faults that may occur with scan-based tests [2][3][4]. To avoid the need for a tester that can apply functional test sequences, the sequences can be applied from an onchip memory as in the case of software-based self-test approaches [5][6][7][8]. Recent interest in functional test sequences can be seen from [9][10][11][12][13][14][15].…”
Section: Introductionmentioning
confidence: 99%