Design framework for an energy-efficient binary convolutional neural network accelerator based on nonvolatile logic

Abstract

Convolutional neural network (CNN) accelerators, particularly binarized CNN (BCNN) accelerators have proven to be effective for several artificial-intelligence-oriented several applications; however, their energy efficiency should be further improved for edge applications. In this paper, a design framework for an energy-efficient BCNN accelerator based on nonvolatile logic is presented. Designing BCNN accelerators using nonvolatile logic allows for the accelerators to exhibit a massively parallel and ultra-low standby power capability. Thus, a new design can be realized for accelerators that is different from that of conventional accelerators based solely on CMOS. Considering this, we discuss a concrete design considerations of nonvolatile BCNN accelerators. In fact, a systematic design flow of the nonvolatile BCNN is established by combining Vivado HLS and standard electronic design automation tools. As a typical design example, a BCNN accelerator for inferring 32 × 32 pixel MNIST dataset is designed using a 65-nm CMOS technology. By the logic-synthesis result, the proposed BCNN accelerator is estimated to consume 94.2% lower power than that of a conventional BCNN accelerator when the frame rate is 30 frames per second.

Image sequence decomposition via sigma-delta cellular neural network having coupled cells

“…This mechanism is radically different from current mainstream artificial neural networks as known as deep neural networks [1][2][3]. Although deep neural networks are most potent in image processing tasks, it is said that their energy efficiency should be improved for edge computing [4].…”

Design of an active-load-localized single-ended nonvolatile lookup-table circuit for energy-efficient binary-convolutional-neural-network accelerator

“…the time when the power supply is temporally turned off) is increased. 50) The total number of MAC operations to infer one input image SC1083-8 © 2022 The Japan Society of Applied Physics is calculated as 294 200, and thus operations per second (OPS) is estimated as 14.9GOPS. In the current situation, the maximum clock frequency is restricted by the switching time of the SOT-MTJ device.…”