Design, Implementation, and Validation of a New Class of Interface Circuits for Latency-Insensitive Design

Li, Chenghong; Collins, Rebecca L.; Sonalkar, Sampada; Carloni, Luca P.

doi:10.1109/memcod.2007.371256

Cited by 19 publications

(11 citation statements)

References 26 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In order to quantify the costs of a LI design methodology we have created a set of LI wrappers and relay stations based on those presented in [14] and implemented them on Stratix IV FPGAs. Example wrappers are shown in Figure 3.…”

Section: Latency Insensitive Design Im-plementationmentioning

confidence: 99%

See 1 more Smart Citation

Quantifying the cost and benefit of latency insensitive communication on FPGAs

Murray

Betz

2014

Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

View full text Add to dashboard Cite

Latency insensitive communication offers many potential benefits for FPGA designs, including easier timing closure by enabling automatic pipelining, and easier interfacing with embedded NoCs. However, it is important to understand the costs and trade-offs associated with any new design style. This paper presents optimized implementations of latency insensitive communication building blocks, quantifies their overheads in terms of area and frequency, and provides guidance to designers on how to generate high-speed and areaefficient latency insensitive systems.

show abstract

Section: Latency Insensitive Design Im-plementationmentioning

confidence: 99%

“…This is surrounded by a wrapper shell which stalls the pearl if one or more inputs are not available, and queues incoming valid data in FIFOs. In [14] stalling was performed by gating the pearl's clock. However, the granularity of clock gating available on FPGAs is very coarse.…”

Section: Baseline Wrappermentioning

confidence: 99%

Quantifying the cost and benefit of latency insensitive communication on FPGAs

Murray

Betz

2014

Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

View full text Add to dashboard Cite

show abstract

“…Its wrapper implementation is shown in Fig. 12(b), which is similar to the design in [20] but is simplified for our situation. In the MG model, given B(p1) = 1 and B(p2) = 3, RS1 and RS2 are implemented as Q1 and Q3.…”

Section: Synthesis Of Lis Using Mbpamentioning

confidence: 99%

Minimizing back pressure for latency insensitive system synthesis

Xue

Shukla

Ravi

2010

Eighth ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE 2010)

View full text Add to dashboard Cite

Most scheduling based latency insensitive designs in the literature focus on systems whose graphical representation is a single strongly connected component (SCC), where a hand-shake based protocol can be replaced by periodic clock gating through ASAP scheduling. However, for systems that are represented as interconnected SCCs, 'back pressure', always implemented as the 'stall' signal in the backward directions between SCCs, is required to prevent overflow. In this paper, we formulate the problem of finding a minimum set of back pressure edges. We show that this problem can be reduced to the Minimum Cost Arborescence (MCA) problem for directed graphs. This allows us to obtain a polynomial time algorithm for synthesizing a minimum cost latency insensitive implementation starting from a synchronous model of the original system. We also show that implementing back pressure edges for every inter-SCC connection, as done in a regular hand-shake based protocol, is inferior for the overall system's throughput. Our approach provides a formal framework for converting a synchronous model into a latency insensitive implementation with a minimum number of inter-SCC back pressure edges and for leveraging periodic clock based scheduling of intra-SCC latency insensitivity.

show abstract

“…The FIC of each channel P i is stored in variable F IC P i (f , g), which is computed by the inner loop (lines 3-10). Then, F IC P i (f , g) is processed based on whether we want to generate the full set of FIC or only SDFIC, which depend only on state variables (lines [11][12][13][14]. The inner loop from lines 3 to 10 performs the main computation of FIC of channel P i .…”

Section: A Background Definitionsmentioning

confidence: 99%

Leveraging Local Intracore Information to Increase Global Performance in Block-Based Design of Systems-on-Chip

Carloni

2009

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

View full text Add to dashboard Cite

Abstract-Latency-insensitive design is a methodology for system-on-chip (SoC) design that simplifies the reuse of intellectual property cores and the implementation of the communication among them. This simplification is based on a system-level protocol that decouples the intracore logic design from the design of the intercore communication channels. Each core is encapsulated within a shell, a synthesized logic block that dynamically controls its operation to interface it with the rest of the SoC and absorb any latency variations on its I/O signals. In particular, a shell stalls a core whenever new valid data are not available on the input channels or a downlink core has requested a delay in the data production on the output channels. We study how knowledge about the internal logic structure of a core can be applied to the design of its shell to improve the overall system-level performance by avoiding unnecessary local stalling. We introduce the notion of functional independence condition (FIC) and present a novel circuit design of a generic shell template that can leverage FIC. We propose a procedure for the logic synthesis of a FIC-shell instance that is only based on the analysis of the intracore logic and does not require any input from the designers. Finally, we present a comprehensive experimental analysis that shows the performance benefits and limited design overhead of the proposed technique. This includes the semicustom design of an SoC, an ultrawideband baseband transmitter, using a 90-nm industrial standard cell library.Index Terms-Finite state machines (FSMs), latency-insensitive design (LID), logic synthesis, sequential logic optimization, system-level design, system-on-chip (SoCs).

show abstract

Design, Implementation, and Validation of a New Class of Interface Circuits for Latency-Insensitive Design

Cited by 19 publications

References 26 publications

Quantifying the cost and benefit of latency insensitive communication on FPGAs

Quantifying the cost and benefit of latency insensitive communication on FPGAs

Minimizing back pressure for latency insensitive system synthesis

Leveraging Local Intracore Information to Increase Global Performance in Block-Based Design of Systems-on-Chip

Contact Info

Product

Resources

About