Design, implementation and verification of 32-Bit ALU with VIO

Devi, Dharmavaram Asha; Sugun, L. Sai

doi:10.1109/icisc.2018.8399122

Cited by 10 publications

(4 citation statements)

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“…D.A. Devi, et al, presented a work on a 32-bit ALU that is planned, simulated, and tested through VIO [14]. The significance of this idea is that, in cases where physical access to I/Os is not possible, we may dynamically test the operation of our design by using the VIO hardware debug IP.…”

Section: Literature Surveymentioning

confidence: 99%

“…The enhancement of the proposed work over the previous work is customized the design of FPAU in 28nm Technology. In the earlier work referred [13], [14], [15] and [16], the design is normal binary 32 bit and 64 bit arithmetic, logic and code conversion operations. All the works are verified with virtual input and output debug IP.…”

Section: Comparison Analysismentioning

confidence: 99%

“…i. In reference [14], a 32-bit ALU was designed and implemented on a Nexys 4 DDR development board and VIO hardware debug IP. ii.…”

Section: Comparison Analysismentioning

confidence: 99%

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Custom Ip Design and Verification for Ieee754 Single Precision Floating Point Arithmetic Unit

Dharmavaram,

2024

AEJ

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The compact and accurate way of representing numbers in a wide range is the advantage of floating-point (FP) representation and computation. The floating-point digital signal processors offer the IPs that should have the features of low power, high performance, and less area in cost-effective designs. The proposed paper demonstrates the design and implementation of a 32-bit floating-point arithmetic unit (FPAU). The arithmetic operations performed by the FPAU are in the IEEE 754 single precision format for FP numbers. Before performing the 32-bit FP arithmetic operations, the input operands are converted to IEEE 754 single precision. In order to make use of this functional unit in the processor designs, the proposed work discuss about the creation of custom IP. The validation and verification of this IP will be done with the Xilinx Vivado Design software. Here, the verification is performed with VIO hardware debug IP and Zed board. This FPAU IP can be used in DSP applications and can also be used as a floating-point arithmetic block in semi-custom microprocessor and microcontroller designs.

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Section: Literature Surveymentioning

confidence: 99%

Section: Comparison Analysismentioning

confidence: 99%

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Custom Ip Design and Verification for Ieee754 Single Precision Floating Point Arithmetic Unit

Dharmavaram,

2024

AEJ

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“…The FPGA based processor designs, verifications of various applications are referred from [15], [16], [17], [18], [19] and [20].…”

Section: Introductionmentioning

confidence: 99%

Design and Implementation of Real Time Data Acquisition System using Reconfigurable SoC

Devi¹,

Savithri²,

Sugun.L³

2020

IJACSA

Self Cite

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System on chip (SoC) technology is widely used for high speed and efficient embedded systems in various computing applications. To perform this task, Application Specific IC (ASIC) based system on chips are generally used till now by spending maximum amount of research, development time and money. However, this is not a comfortable choice for low and medium-level capacity industries. The reason is, with ASIC or standard IC design implementation, it is very difficult task where quick time to market, upgradability and flexibility are required. Therefore, better solution to this problem is design with reconfigurable SoCs. Therefore, FPGAs can be replaced in the place of ASICs where we can have more flexible and reconfigurable platform than ASIC. In the embedded world, in many applications, accessing and controlling are the two important tasks. There are several ways of accessing the data and the corresponding data acquisition systems are available in the market. For defence, avionics, aerospace and automobile applications, high performance and accurate data acquisition systems are desirable. Therefore, an attempt is made in the proposed work, and it has been discussed that how a reconfigurable SoC based data acquisition system with high performance is designed and implemented. It is a semicustom design implemented with Zynq processing system IP, reconfigurable 7-series FPGA used as programmable logic, hygro, ambient light sensor and OLEDrgb peripheral module IPs. All these sensor and display peripheral modules are interfaced with processing unit via AXI-interconnect. The proposed system is a reconfigurable SoC meant for high-speed data acquisition system with an operating frequency of 100MHz. Such system is perfectly suitable for high speed and economic real time embedded systems.

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Monitoring and Controlling of ICU Environmental Status with WiFi Network Implementation on Zynq SoC

Devi¹,

Savithri

Babu³

2021

Inventive Systems and Control

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Design, implementation and verification of 32-Bit ALU with VIO

Cited by 10 publications

References 0 publications

Custom Ip Design and Verification for Ieee754 Single Precision Floating Point Arithmetic Unit

Custom Ip Design and Verification for Ieee754 Single Precision Floating Point Arithmetic Unit

Design and Implementation of Real Time Data Acquisition System using Reconfigurable SoC

Monitoring and Controlling of ICU Environmental Status with WiFi Network Implementation on Zynq SoC

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