Design Insights of Nanosheet FET and CMOS Circuit Applications at 5-nm Technology Node

Gate-all around (GAA) device is one of the cutting-edge technologies and the advantages of these devices can be improved by incorporating the dual material (DM) and graded channel (GC) techniques. This manuscript investigates for the first time, the performance analysis of DMGC CGAA FET and circuit applications such as inverter, NAND, NOR, ring oscillator and 6T SRAM. It has been found that the Ioff, SS, DIBL, Ion/Ioff ratio are enhanced by an amount of 96.93%, 19.49%, 51.26%, 96.98% respectively for DMGC CGAA FET when compared to SMGC CGAA FET. Single-k (SiO2) and dual-k (SiO2+HfO2) techniques are also utilized here to analyse the device performance and dual-k recorded better performance in comparison with single-k owing to reduced off-state currents. It is noticed that delay has been reduced greatly for Inverter, NAND, and NOR by an amount of 51.93%, 11.25%, and 10.07% respectively for dual-k when compared to single-k DMGC CGAA FET. The frequency of oscillations for Ring Oscillator is improved by 69.7% with dual-k than single-k. Further, the obtained results of SRAM are compared with the existing literatures and noticed that the proposed DMGC CGAA FET outperforms the other works making the device a potential candidature for high performance applications.

Section: T E O T T K39 1 High K Imentioning

confidence: 99%

Circuit Level Analysis of a Dual Material Graded Channel (DMGC) Cylindrical Gate All Around (CGAA) FET at Nanoscale Regime

Mudidhe¹,

Nistala²

2023

“…Furthermore, the propagation delay (τ p ), energy delay product (EDP), and power delay product are calculated as given in Ref. 6 The τ p of 1.551 ps, EDP of 2.196 × 10 −28 Js and PDP of 141.6 × 10 −18 J are obtained for dual-k NSFET based inverter.…”

Section: Circuit Analysismentioning

confidence: 99%

“…Further, the "C" value of 1 μF is considered at the output stage. 6 The transient response of the CS amplifier is evaluated for a time duration of 100 ns, as shown in Fig. 14b.…”

Section: Circuit Analysismentioning

confidence: 99%

“…Nowadays, the technology-driven world is moving towards artificial intelligence (AI) and machine learning (ML) based applications leading to optimum utilization of resources such as power, area, and speed, 1,2 The Integrated circuits (IC) play a crucial role while deciding the performance of a whole system, 3,4 The complementary metal oxide semiconductor (CMOS) technology is a major breakthrough in semiconductor technology, which brought revolutionary changes in technology. The metal oxide semiconductor field effect transistor (MOSFET) is the building block of CMOS technology and is widely employed in IC designs in the 21st century, 5,6 Moreover, MOSFETs became promising candidates as they offer high performance and consume less power. To meet the needs of technology, it is highly essential to downscale the transistor sizes to lower technology nodes, 7,8 According to Moore's law, for every eighteen months, the number of transistors on a chip gets doubled.…”

mentioning

confidence: 99%

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Spacer Engineering on Nanosheet FETs towards Device and Circuit Perspective

Kumari,

Sreenivasulu,

Ajayan

et al. 2023

Self Cite

For the first time, a nanosheet field effect transistor (NS FET) performance is demonstrated by incorporating various device engineering at both device and circuit levels. Various device topologies like lightly-doped drain/source, underlap, single and dual-k spacer are explored and the performance is compared with conventional NS FET. The NS FET with dual-k spacer is able to reduce the off current by 13.6× compared to the traditional NS FET. Further, the dual-k spacer offered good electrostatic performance and high switching ratio. Moreover, the analog/RF figures of merit are assessed for various device configurations. Though the dual-k spacer outperforms in terms of DC and analog metrics, the conventional NS FET can offer better RF metrics owing to the high current. Further, circuit level analysis is carried out using the Cadence tool for mixed circuit applications. The crucial circuits for IC design such as inverter, ring oscillator and common source (CS) amplifier are designed and evaluated the performance. The NS FET with dual-k spacer offers a gain of 1.815 for the CS amplifier and an oscillation frequency of 34.09 GHz for the 3-stage ring oscillator. The results will give insights into the performance of NS FET with various device architectures

“…As the gate surrounds the channel, the performance of the transistor increased substantially and made it possible to continue Moore's law further. 27 The GAA Nanosheet FET (NSFET) became a strong contender to FinFET for sub-5-nm nodes and offered superior performance over FinFETs. It is experimentally demonstrated that by incorporating NSFETs instead of FinFETs, a 30% higher effective width can be achieved under the same footprint.…”

mentioning

confidence: 99%

Impact of Scaling on Nanosheet FET and CMOS Circuit Applications

Neelam

Sreenivasulu

Pothupogu

2023

Self Cite

The impact of scaling on the gate all around the nanosheet field effect transistor (NSFET) was studied in detail at sub-5-nm nodes for digital and analog/RF applications. When LG is scaled from 20 to 5 nm, ION is improved by 2.1×, IOFF increases by three orders of magnitude, SS increases by 27%, DIBL is increased by 4×, and a Vth roll off of 41 mV is noticed. Further, an enhancement of 3.65× was noticed in cut-off frequency (fT) with scaling of LG from 20 to 5 nm. The complimentary metal oxide semiconductor (CMOS) inverter and ring oscillator’s performance was studied in detail with LG scaling. With LG scaling from 20 to 5 nm, the inverter performance metrics like switching current is increased by 3.87×, propagation delay (τP), energy delay product and power delay product are reduced by 65%, 5.5× and 1.95×, respectively. Moreover, the ring oscillator offers superior performance with an oscillation frequency of 98.05 GHz when LG is scaled to 5nm, which is 157% more than fOSC at LG of 20 nm. Thus the analyses reveal the scaling capability of NSFET at both device and circuit levels for sub-5-nm nodes.