Design Issues in Next-Generation Merchant Switch Fabrics

Audigier, François; Minkenberg, Cyriel; Iliadis, Ilias; Engbersen, Ton; Gusat, Mitch; Gramsamer, Ferdinand; Luijten, Ronald P.

doi:10.1109/tnet.2007.909727

Cited by 29 publications

(20 citation statements)

References 33 publications

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“…For instance, these models have dealt with flow rate equilibria [1]- [3], router buffer sizing [12], [14], [16], [17], TCP dynamics [13], [18], TCP fairness [2], [3], [23], Weighted Fair Queueing (WFQ) [19], and Active Queue Management (AQM) analysis [20], [21]. Unfortunately, outputqueued switching cannot be implemented in high-speed routers because of its required memory speedup [22]. Therefore, we will analyze the more realistic input-queued routers and their associated switch scheduling algorithms.…”

Section: B Related Workmentioning

confidence: 99%

Modeling the interactions of congestion control and switch scheduling

Shpiner

Keslassy

2011

Computer Networks

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Abstract-In this paper, we study the interactions of user-based congestion control algorithms and router-based switch scheduling algorithms. We show that switch scheduling algorithms that were designed without taking into account these interactions can exhibit a completely different behavior when interacting with feedbackbased Internet traffic. Previous papers neglected or mitigated these interactions, and typically found that flow rates reach a fair equilibrium. On the contrary, we show that these interactions can lead to extreme unfairness with temporary flow starvation, as well as to large rate oscillations. For instance, we prove that this is the case for the MWM switch scheduling algorithm, even with a single router output and basic TCP flows. We also show that the iSLIP switch scheduling algorithm achieves fairness among ports, instead of fairness among flows. Finally, we fully characterize the network dynamics for both these switch scheduling algorithms.

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Section: B Related Workmentioning

confidence: 99%

Modeling the interactions of congestion control and switch scheduling

Shpiner

Keslassy

2011

Computer Networks

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“…However, since the linecard and switch fabric racks are separated to decrease the power consumption per rack [18], this assumption does not hold in practice, and the round-trip communication time cannot be neglected in front of a time-slot. For instance, the round-trip propagation time can last up to 600 ns, assuming inter-rack optical fibers with a maximum length of 60 meters and a propagation speed of c/n = 2·10 8 m/s [20]. On the other hand, a time-slot lasts 2 ns, assuming 64-byte segmented packets in next-generation OC-3072 lines (160 Gbps) with a 60% segmentation overhead [21].…”

Section: A Backgroundmentioning

confidence: 99%

“…On the other hand, a time-slot lasts 2 ns, assuming 64-byte segmented packets in next-generation OC-3072 lines (160 Gbps) with a 60% segmentation overhead [21]. Therefore, a round-trip time is clearly not negligible in front of a time-slot -in fact, it lasts some 300 time-slots, not even counting Serializer/Deserializer (SERDES) delays, and this number keeps increasing proportionally to the line rate [20].…”

Section: A Backgroundmentioning

confidence: 99%

“…In addition, in order to obtain a high total throughput, switches often need to use multiple crossbars in parallel (by bit-slicing, time-slicing, or using multiple-stage switching). Therefore, switch designers can use these many parallel buffered crossbars to increase the total buffer size or reduce the buffer size per chip [12], [20]. For instance, keeping our example of N = 128 ports at 160 Gbps with a 60% segmentation overhead, we would need a total switch throughput of 34 Tbps.…”

Section: B the Cq Switch: Architecture And Implementationmentioning

confidence: 99%

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The Crosspoint-Queued Switch

2009

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Abstract-This paper calls for rethinking packet-switch architectures by cutting all dependencies between the switch fabric and the linecards. Most single-stage packet-switch architectures rely on an instantaneous communication between the switch fabric and the linecards. Today, however, this assumption is breaking down, because effective propagation times are too high and keep increasing with the line rates.In this paper, we argue for a self-sufficient switch fabric by moving all the buffering from the linecards to the switch fabric. We introduce the crosspoint-queued (CQ) switch, a new bufferedcrossbar switch architecture with large crosspoint buffers and no input queues, and show how it can be readily implemented in a single SRAM-based chip using current technology. For a crosspoint buffer size of one, we provide a closed-form throughput formula for all work-conserving schedules under uniform Bernoulli i.i.d. arrivals. Furthermore, we study the performance of the switch for larger buffer sizes and show that it nearly behaves as an ideal output-queued switch. Finally, we confirm our results using synthetic as well as trace-based simulations.

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“…INTRODUCTION Buffered crossbar switches have recently attracted considerable attention as the next generation of high speed interconnects [1]. They are a special type of crossbar switches with an exclusive buffer at each crosspoint of the crossbar, which has been feasible with advances in modern VLSI technology to integrate miniaturized on-chip memories.…”

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confidence: 99%

Reducing Crosspoint Buffers for Performance Guaranteed Asynchronous Crossbar Scheduling

Karimi

Sun

Pan

et al. 2010

2010 IEEE Global Telecommunications Conference GLOBECOM 2010

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Abstract-Buffered crossbar switches are special crossbar switches with an exclusive buffer at each crosspoint. They demonstrate unique advantages over traditional unbuffered crossbar switches, such as asynchronous scheduling and variable length packet handling. However, since crosspoint buffers are expensive on-chip memories, it is desired that each crosspoint has only a small buffer. In this paper, we propose a scheduling algorithm called Fair Asynchronous Segment Scheduling (FASS) for buffered crossbar switches, which reduces the crosspoint buffer size by dividing packets into shorter segments before transmission. FASS also provides tight constant performance guarantees by emulating the ideal Generalized Processor Sharing (GPS) model. Furthermore, FASS requires no speedup for the crossbar, lowering the hardware cost and improving the switch capacity. By theoretical analysis, we prove that FASS is strongly stable and therefore achieves 100% throughput. We also calculate the size bound for the crosspoint buffers and the reassembly buffers at output ports. Moreover, we show that FASS provides bounded delay guarantees. Finally, we present simulation data to verify the analytical results.

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Design Issues in Next-Generation Merchant Switch Fabrics

Cited by 29 publications

References 33 publications

Modeling the interactions of congestion control and switch scheduling

Modeling the interactions of congestion control and switch scheduling

The Crosspoint-Queued Switch

Reducing Crosspoint Buffers for Performance Guaranteed Asynchronous Crossbar Scheduling

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