Design Margin Exploration of Spin-Transfer Torque RAM (STT-RAM) in Scaled Technologies

Chen, Yiran; Wang, Xiaobin; Li, Hai; Xi, Hongwei; Yan, Yuan; Zhu, Wenzhong

doi:10.1109/tvlsi.2009.2032192

Cited by 76 publications

(26 citation statements)

References 17 publications

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“…Access transistor sizing has been investigated in [7,13], effect of process variation as well as write pulse width has been studied in [13,14,28] and voltage boosting of WL has been considered in [13,29]. Here, we also study the read reliability and investigate the effect of combination of write pulse width and voltage boosting on the write reliability.…”

Section: Circuit-level Techniques For Reducing Errormentioning

confidence: 99%

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Improving reliability of non-volatile memory technologies through circuit level techniques and error control coding

Yang

Emre

Cao

et al. 2012

EURASIP J. Adv. Signal Process.

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Non-volatile resistive memories, such as phase-change RAM (PRAM) and spin transfer torque RAM (STT-RAM), have emerged as promising candidates because of their fast read access, high storage density, and very low standby power. Unfortunately, in scaled technologies, high storage density comes at a price of lower reliability. In this article, we first study in detail the causes of errors for PRAM and STT-RAM. We see that while for multi-level cell (MLC) PRAM, the errors are due to resistance drift, in STT-RAM they are due to process variations and variations in the device geometry. We develop error models to capture these effects and propose techniques based on tuning of circuit level parameters to mitigate some of these errors. Unfortunately for reliable memory operation, only circuit-level techniques are not sufficient and so we propose error control coding (ECC) techniques that can be used on top of circuit-level techniques. We show that for STT-RAM, a combination of voltage boosting and write pulse width adjustment at the circuit-level followed by a BCH-based ECC scheme can reduce the block failure rate (BFR) to 10 -8 . For MLC-PRAM, a combination of threshold resistance tuning and BCH-based product code ECC scheme can achieve the same target BFR of 10 -8. The product code scheme is flexible; it allows migration to a stronger code to guarantee the same target BFR when the raw bit error rate increases with increase in the number of programming cycles.

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Section: Circuit-level Techniques For Reducing Errormentioning

confidence: 99%

“…Gate level (WL) voltage boosting has been investigated in [13,29] to reduce the write-1 latency of STT-RAM. It is an effective way of increasing the drive current of access transistor which leads to reduction in latency.…”

Section: Effect Of Voltage Boostingmentioning

confidence: 99%

Improving reliability of non-volatile memory technologies through circuit level techniques and error control coding

Yang

Emre

Cao

et al. 2012

EURASIP J. Adv. Signal Process.

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“…[1][2][3][4][5][6][7][8][9] While standby power is dramatically reduced because of non-volatility of MTJs, the writing energy utilizing STT is at best sub-pJ/bit which is still larger than their semiconductor memory counterparts. [10][11][12] One of the alternative low power writing schemes in MTJs is by means of voltage controlled magnetic anisotropy (VCMA).…”

Section: Introductionmentioning

confidence: 99%

Role of CoFeB thickness in electric field controlled sub-100 nm sized magnetic tunnel junctions

2017

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We report a comprehensive study on the role of the free layer thickness (tF) in electric-field controlled nanoscale perpendicular magnetic tunnel junctions (MTJs), comprising of free layer structure Ta/Co40Fe40B20/MgO, by using dc magnetoresistance and ultra-short magnetization switching measurements. Focusing on MTJs that exhibits positive effective device anisotropy (Keff), we observe that both the voltage-controlled magnetic anisotropy (ξ) and voltage modulation of coercivity show strong dependence on tF. We found that ξ varies dramatically and unexpectedly from ∼−3 fJ/V-m to ∼−41 fJ/V-m with increasing tF. We discuss the possibilities of electric-field tuning of the effective surface anisotropy term, KS as well as an additional interfacial magnetoelastic anisotropy term, K3 that scales with 1/tF2. Voltage pulse induced 180° magnetization reversal is also demonstrated in our MTJs. Unipolar switching and oscillatory function of switching probability vs. pulse duration can be observed at higher tF, and agrees well with the two key device parameters — Keff and ξ.

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“…Even when writing currents of the same magnitude are applied to the same MTJ cell, the switching of the MTJ-state occurs after different delays. In conventional write-schemes which use fixedpulse-width pulses [6,10,12], the pulse-width should be set to be longer than the longest switching-time of the cell to be accommodated [10,11]. This can be much longer than the average switching time; therefore, a significant power can be wasted by the continuation of the write-process long after the switching has already occurred.…”

Section: Introductionmentioning

confidence: 99%

Low-Power Write-Circuit with Status-Detection for STT-MRAM

Shin

Park³

2016

JSTS:Journal of Semiconductor Technology and Science

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Abstract-We report a STT-MRAM write-scheme, in which the length of the write-pulse is determined dynamically by sensing the status of MTJ cells. The proposed scheme can reduce the power consumption by eliminating unnecessary writing current after the switching has occurred. We also propose a reference cell design, which is optimized for the use in writecircuits. The performance of the proposed circuit was verified by SPICE level simulations of the circuit implemented in a 0.13 μm CMOS process.

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Design Margin Exploration of Spin-Transfer Torque RAM (STT-RAM) in Scaled Technologies

Cited by 76 publications

References 17 publications

Improving reliability of non-volatile memory technologies through circuit level techniques and error control coding

Improving reliability of non-volatile memory technologies through circuit level techniques and error control coding

Role of CoFeB thickness in electric field controlled sub-100 nm sized magnetic tunnel junctions

Low-Power Write-Circuit with Status-Detection for STT-MRAM

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