Design methodologies for low-power asynchronous-logic digital systems

Abstract

Asynchronous design has been an active area of research since the 1950s, but has hitherto yet to achieve widespread use or acceptance. This is largely because several major problems continue to persist that inhibit its acceptance in the very large-scale integration industry as a viable alternative to the prevalent synchronous design. This thesis addresses one such problem: how to reduce the circuit area and power dissipation of asynchronous control networks. Three main contributions are made in this thesis to the design of asynchronous pipelines with low asynchronous control overheads. First, a synthesis method for asynchronous pipelines is proposed that adopts a coarse-grain approach to the synthesis of asynchronous control networks, thereby leading to low asynchronous control overhead pipelines. It also has the advantages of offering a largely transparent modeling style for asynchronous communication and ease for integration into the conventional synchronous design flow. The efficacy of the proposed synthesis method is demonstrated through the design of a Reed-Solomon error detector and an interpolated finite-impulse-response filterbank-the simulated circuit implementations based on the proposed synthesis method dissipate on the average 31% less energy than those implemented by comparable reported synthesis methods. Second, two optimization methods are proposed for reducing the circuit area and power dissipation of asynchronous control networks while satisfying pipeline throughput constraints. The first proposed optimization method-handshake component fusion-is a form of peephole optimization that iteratively selects a pair of handshake components that share input channel sources or output channel destinations and replaces them with a single component. The second proposed optimization method-optimal decoupling-searches for the optimal mix of handshake components of different degree of concurrency in a given asynchronous control network with the objective of incurring the least circuit area and power dissipation for the control network, while satisfying a throughput constraint. The proposed optimization methods are applied on three designs and are found to reduce the asynchronous control networks' transistor count and energy dissipation by, on the average, 28% and 36%, respectively. A fundamental requirement of the proposed optimization methods is that the minimal-support S-invariants for the Petri net models of the asynchronous control networks are recomputed at each optimization iteration. vii ATTENTION: The Singapore Copyright Act applies to the use of this document. Nanyang Technological University Library Arising from the fundamental requirement mentioned above, the third main contribution of the thesis is a fast and memory-efficient algorithm for computing all minimal-support S-invariants for ordinary Petri nets. Based on a large number of test problems, the proposed algorithm is demonstrated to be at least 2.2x faster and 1.8x more memory efficient than reported algorithms. The proposed synthesis method, ...

Asynchronous Control Network Optimization Using Fast Minimum-Cycle-Time Analysis

“…Our error detector is based on the handshake components we developed for general asynchronous systems [30]. Fig.…”

Design implementation low energy fast fourier transform/inverse fast fourier transform (FFT/IFFT) processor based on asynchronous-logic

“…Technological University (NTU) research effort on async design, including the development of sophisticated async EDA tools (async design compiler [53]), async library cells, and the integration of the EDA tools and a cell library. The specific research effort in this PhD program delineated in this thesis pertains to an exploitation of the low power/energy attributes of the async approach to realize a relatively complex digital signal processing circuit (> 50K transistors) − an async FFT/inverse FFT (FFT/IFFT) processor for advanced audio devices including hearing aids.…”

“…This is largely due to the lack of advanced async EDA tools and established async library cells. With more advanced async tools [53], [91], [92] and library cells developed in the future, the design effort of async design is likely to be reduced. Nonetheless, async designs have yet to be accepted as a serious alternative to sync designs and the maturity of async designs will likely lag sync designs in the immediate term.…”