Design Methodology Of Deep Submicron CMOS Devices For 1V Operation

Abstract

IntroductionIt has been already clarified that, in down scaling of device dimensions, power-supply voltage (Vcc) for CMOS devices can be reduced from 5V to 2.5V without sacrificing performance trend ancl device reliability [']. Moreover, an operating voltage must be steadily reduced from power dissipation point of view, according to prospect for future CMOS design in deep-submicron era. On the other hand, the various CMOS chips for battery back up system such as a watch, a portable radio and stereo already exist at 1-1 5V operation. However, such CMOS chips compromise their performance, since the threshold voltage is constant for any generation chips, in order to preserve standby power. Therefore, a new device design is required in order to offer low voltage operated CMOS device without any speed loss.111 this paper, design method for high performance deepsubmicron CMOS operated at around 1V has been proposed, together with discussion on threshold voltage limitation and suppression of parasitic effects. Based on above consideration, a 1V operated 0.15pm CMOS was fabricated and evaluated. As a result, 50psec at 1V operation for the CMOS ring oscillator at room temperature has been verified. Figure 1 shows threshold voltage (Vth) dependence of the gate delay time of the CMOS inverter with F/O=l. As Vth approaches toward Vcc, delay time increases rapidly corresponding to drastic reduction of MOSFET's current. It is necessary to decrease the threshold voltage as low as possible to achieve high circuit performance. On the contrary, lowering Vth causes large increase of standby power as shown Fig.2. However, high speed application can accept standby power below O.lW, since a high speed cblip does not require battery back up use. Vth reduction also cau!;es insufficient noise margin. Figure 2 shows lower limit of the threshold voltage determined by noise margin (NM), which was defined as (Vo -VoL) /(VIH-VIL) and simulated with Sodini for various%cc. As c early indicated in Fig.2, the threshold voltage can be lowered with reduction of power supply voltage, ancl the lower limit is about 15% of Vcc. Reduction of Threshold Voltage for Low Voltage Operation Parasitic Capacitance and ResistanceThe parasitic capacitance of CMOS LSI consists of junction capacitance C,, gate oxide capacitance CO,, and wiring capacitance Cw. Figure 3 shows power-supply voltage dependence of the percentage that each parasitic capacitance shares in typical load capacitance of LSI circuits. C is inversely proportional to square root of 'Jcc, while CO, and dw do not depend on it. As a result, the total parasitic capacitance 1s Increased, and further, C, becomes one of the dominant parasitics with lowering operation voltage. Therefore, reduction of C, is a key issue for achieving high speed circuit operation at low voltage such as 1V. In order to reduce (Z,, 'spot punch through stopper ion implantation' can be introduced. The implantation is adjusted to junction depth and restricted xverly under channel area, excluding junction area, as shown in Fig.4....

Dynamic threshold pass-transistor logic for improved delay at lower power supply voltages

“…Acceptable values of are typically between 1/4 and 1/5 [3]- [5]. Even with a threshold as low as 0.2 V [5], [6], it will be difficult to maintain decent performance for a supply lower than 1 V with conventional circuitry. Such reasoning led to the predictions published in the 1994 SIA Roadmap and reprinted in Table I. The above discussion was based on a critical assumption-that we use the same threshold voltage in both the onand off-state.…”

SIGNAL-PATH-LEVEL DUAL-Vt ASSIGNMENT FOR LEAKAGE POWER REDUCTION

“…21 Thus, it is important to decide the value of high threshold voltage. If the value of the V THhigh is close to the value of the V THlow , then there will be much more signal-paths that can be changed into V THhigh , and it also gives small leakage current improvement.…”