Design Methodology of FIR Filtering IP Cores for dsp based Systems

Abstract

In this paper, Intellectual Property (IP) core for unfolded direct form Finite Impulse Response (FIR) filter is proposed for reusable system design. The designed core is programmable and parameterized in terms of data bits, coefficient bits, filter order and type of filter (Low pass, High pass, Band pass etc). The IP core is described in Verilog HDL and the core programmability and parameterization features are tested by changing type of filters (Low pass, High pass and Band pass) and taps of filters. The core is synthesized on Spartan 2S50E FPGA for 8bit and 16bit widths using an 11 taps FIR Filter. Design methodology and core architecture are described in detail and favorable results for area/speed performance are reported.

Implementation of a LMS filter on FPGA employing extremeDSP and smart IP-core design

“…It's based on the principle of Minimum Mean Square Error (MMSE) and steepest descent algorithm and aims to determine the optimal weight vector. ( 1) w n is estimated according to the following recursion:…”