Design metrics for blind ADC-based wireline receivers

Abstract

ADC-based receivers use an ADC in the front end to convert the incoming signal to digital where significant equalization can be done in digital domain. These receivers can be classified as phase-tracking and blind architectures. In the former, the VCO phase is controlled through a feedback loop so as to sample the received data in the middle of the data eye. In the latter, the received signal is sampled with a blind clock, i.e. not in a loop, and the data at the center is obtained by data processing techniques such as data interpolation and extrapolation. This paper compares the two architectures in terms of their design complexity and cost, and derives equations that relate the required ADC resolution to channel loss and to the characteristics of the FFE/DFE that follow the ADC.

A 3x blind ADC-based CDR for a 20 dB loss channel

“…The DI block outputs 10-12 digits, depending on the position of . This variable length output is absorbed in the elastic buffer following the CDR [21].…”

4×, 3‐level, blind ADC‐based receiver

“…These high resolutions were needed for the digital blocks following the ADCs to accurately recover the value and the phase of the data. The ADC resolution also determines the amount of digital equalisation that can be achieved in the digital domain [9].…”