Design, modeling, and characterization of passive channels for data rates of 50 Gbps and beyond

Abstract

The design of interconnects for links operating at 50 Gbps and beyond is very challenging. The loss, dispersion, and discontinuities along the signaling path have to be minimized over a wide frequency range. Frequency dependent material properties and surface roughness has to be accurately considered. The impacts of short via stubs that are ignored at lower data rates can severely degrade the signals when operating at higher data rates. In order to provide ways to mitigate these effects and optimize the performance of the system, it is primarily essential to correctly model and characterize the passive channel. In this paper, the modeling and characterization techniques that guarantee successful designs of passive channels for data rates of 50 Gbps and beyond will be presented. Detailed studies and measurement results on the effects of short via stubs are also presented. IntroductionMemory bandwidth requirements for high performance computing, data centers, servers and storages, driven by internet in general and multi-core memory and processors architectures in particular, are rapidly increasing to meet the performance demands of today's applications [1]-[2]. The high bandwidth necessitates a large increase in the interface data rate and width.The design of high-speed links that operate at data rate exceeding 50 Gbps is necessary to support Terabit backplane systems. In the past, the increase the performance of the input/output (I/O) circuits and the use of more complex equalization, complicated coding and modulation and other signal processing techniques have been able to sustain the growth of data rate. However, the electronic and I/O power consumption significantly increases with increasing the interface speed. Thus, the link data rate increase cannot only come from circuit design and process improvements. To improve and extend the reach of copper-based interconnects, several improvement have been suggested including highspeed channel design using low-loss dielectric, smooth copper surfaces, improved connectors and packages [3]- [4].The printed circuit boards (PCB) where the longest signal traces commonly found and where the signal is significantly attenuated impose limitation on the supported speed. In order to predict and optimize the performance of high-speed links operating at 50 Gbps and beyond, it is essential to accurately model and characterize the interconnect systems, such as long traces in backplanes. The models of interconnects have to be broadband and include high frequency effects that were not critical at lower data rates [5]. For higher data rates, proper identification of the frequency-dependent properties of the

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