Design of 10-bit 10MS/s Time-Interleaved Flash-SAR ADC Using Sharable MDAC

Do, Sung-Han; Oh, Seong-Jin; Seo, Dong-Hyeon; Lee, Juri; Lee, Kang-Yoon

doi:10.5573/ieiespc.2015.4.1.059

IEIE Transactions on Smart Processing and Computing

2015

DOI: 10.5573/ieiespc.2015.4.1.059

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Design of 10-bit 10MS/s Time-Interleaved Flash-SAR ADC Using Sharable MDAC

Sung-Han Do¹,

Seong-Jin Oh²,

Dong-Hyeon Seo³

et al.

Abstract: This paper presents a 10-bit 10 MS/s Time-Interleaved Flash-SAR ADC with a shared Multiplying DAC. Using shared MDAC, the total capacitance in the SAR ADC decreased by 93.75%. The proposed ADC consumed 2.28mW under a 1.2V supply and achieved 9.679 bit ENOB performance. The ADC was implemented in 0.13mm CMOS technology. The chip area was 760 ´ 280 mm 2 .

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Cited by 4 publications

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Whole Frame Error Concealment with an Adaptive PU-based Motion Vector Extrapolation for HEVC

Kim¹,

Lee²,

Oh³

2015

IEIE Transactions on Smart Processing and Computing

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Abstract:Most video services are transmitted in wireless networks. In a network environment, a packet of video is likely to be lost during transmission. For this reason, numerous error concealment (EC) algorithms have been proposed to combat channel errors. On the other hand, most existing algorithms cannot conceal the whole missing frame effectively. To resolve this problem, this paper proposes a new Adaptive Prediction Unit-based Motion Vector Extrapolation (APMVE) algorithm to restore the entire missing frame encoded by High Efficiency Video Coding (HEVC). In each missing HEVC frame, it uses the prediction unit (PU) information of the previous frame to adaptively decide the size of a basic unit for error concealment and to provide a more accurate estimation for the motion vector in that basic unit than can be achieved by any other conventional method. The simulation results showed that it is highly effective and significantly outperforms other existing frame recovery methods in terms of both objective and subjective quality.

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Whole Frame Error Concealment with an Adaptive PU-based Motion Vector Extrapolation for HEVC

Kim¹,

Lee²,

Oh³

2015

IEIE Transactions on Smart Processing and Computing

View full text Add to dashboard Cite

show abstract

Performance Analysis of HEVC Parallelization Methods for High-Resolution Videos

Ryu¹,

Ahn²,

Mok³

et al. 2015

IEIE Transactions on Smart Processing and Computing

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A Single Inductor Dual Output Synchronous High Speed DC-DC Boost Converter using Type-III Compensation for Low Power Applications

Hayder¹,

Park²,

Kim³

et al. 2015

IEIE Transactions on Smart Processing and Computing

Self Cite

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This paper presents a high speed synchronous single inductor dual output boost converter using Type-III compensation for power management in smart devices. Maintaining multiple outputs from a single inductor is becoming very important because of inductor the sizes. The uses of high switching frequency, inductor and capacitor sizes are reduced. Owing to synchronous rectification this kind of converter is suitable for SoC. The phase is controlled in time sharing manner for each output. The controller used here is Type-III, which ensures quick settling time and high stability. The outputs are stable within 58µs.The simulation results show that the proposed scheme achieves a better overall performance. The input voltage is 1.8V, switching frequency is 5MHz, and the inductor used is 600nH. The output voltages and powers are 2.6V& 3.3V and 147mW&, 230mW respectively.

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Design of 10-bit 10MS/s Time-Interleaved Flash-SAR ADC Using Sharable MDAC

Cited by 4 publications

References 6 publications

Whole Frame Error Concealment with an Adaptive PU-based Motion Vector Extrapolation for HEVC

Whole Frame Error Concealment with an Adaptive PU-based Motion Vector Extrapolation for HEVC

Performance Analysis of HEVC Parallelization Methods for High-Resolution Videos

A Single Inductor Dual Output Synchronous High Speed DC-DC Boost Converter using Type-III Compensation for Low Power Applications

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