Design of 3-Bit ADC in 0.18 µm CMOS Process

Marufuzzaman, Mohammad; Abidin, Syarizal Z.; Reaz, Mamun Bin Ibne; Rahman, Labonnah Farzana

doi:10.11591/telkomnika.v12i7.5539

Cited by 2 publications

(2 citation statements)

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“…data conversion speed, precision & power consumption [4]. Comaprators are the most essential component of ADC's as its precision significantly defines the working genre of these circuits [5]. As to attain these high-performance parameters new techniques are evolving which led to more complex and heavy architectures.…”

Section: Introductionmentioning

confidence: 99%

Analysis of CMOS Comparator in 90nm Technology with Different Power Reduction Techniques

Khatak

Kumar

Dhull

2018

IJECE

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To reduce power consumption of regenerative comparator three different techniques are incorporated in this work. These techniques provide a way to achieve low power consumption through their mechanism that alters the operation of the circuit. These techniques are pseudo NMOS, CVSL (cascode voltage switch logic)/DCVS (differential cascode voltage switch) & power gating. Initially regenerative comparator is simulated at 90 nm CMOS technology with 0.7 V supply voltage. Results shows total power consumption of 15.02 μW with considerably large leakage current of 52.03 nA. Further, with pseudo NMOS technique total power consumption increases to 126.53 μW while CVSL shows total power consumption of 18.94 μW with leakage current of 1270.13 nA. More then 90% reduction is attained in total power consumption and leakage current by employing the power gating technique. Moreover, the variations in the power consumption with temperature is also recorded for all three reported techniques where power gating again show optimum variations with least power consumption. Four more conventional comparator circuits are also simulated in 90nm CMOS technology for comparison. Comparison shows better results for regenerative comparator with power gating technique. Simulations are executed by employing SPICE based on 90 nm CMOS technology.

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Section: Introductionmentioning

confidence: 99%

Analysis of CMOS Comparator in 90nm Technology with Different Power Reduction Techniques

Khatak

Kumar

Dhull

2018

IJECE

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“…To meet the specifications, several techniques and ADC architectures have been proposed. Parallel (flash) ADC is by far the fastest and conceptually simplest has been reported [1]. The drawbacks of this architecture are the resolution is limited by circuit complexity, high power dissipation, and comparator and reference mismatch.…”

Section: Introductionmentioning

confidence: 99%

High Speed and Low Pedestal Error Bootstrapped CMOS Sample and Hold Circuit

Setiabudi¹,

Tamura²,

Tanno³

2018

IJECE

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<p>A new high speed, low pedestal error bootstrapped CMOS sample and hold (S/H) circuit is proposed for high speed analog-to-digital converter (ADC). The proposed circuit is made up of CMOS transmission gate (TG) switch and two new bootstrap circuits for each transistor in TG switch. Both TG switch and bootstrap circuits are used to decrease channel charge injection and on-resistance input signal dependency. In result, distortion can be reduced. The decrease of channel charge injection input signal dependency also makes the minimizing of pedestal error by adjusting the width of NMOS and PMOS of TG switch possible. The performance of the proposed circuit was evaluated using HSPICE 0.18-m CMOS process. For 50 MHz sinusoidal 1 V peak-to-peak differential input signal with a 1 GHz sampling clock, the proposed circuit achieves 2.75 mV maximum pedestal error, 0.542 mW power consumption, 90.87 dB SNR, 73.50 SINAD which is equal to 11.92 bits ENOB, -73.58 dB THD, and 73.95 dB SFDR.</p>

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Design of 3-Bit ADC in 0.18 µm CMOS Process

Cited by 2 publications

References 0 publications

Analysis of CMOS Comparator in 90nm Technology with Different Power Reduction Techniques

Analysis of CMOS Comparator in 90nm Technology with Different Power Reduction Techniques

High Speed and Low Pedestal Error Bootstrapped CMOS Sample and Hold Circuit

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