Design of 32-bit cell-based carry-save combinational multiplier with reduced area and propagation delay

Abstract

In Very Large Scale Integrated (VLSI) and Digital Signal Processing (DSP) applications, a Conventional Combinational Multiplier uses a lot of hardware and propagation delay, and that is one of the main issues. The delay is determined by the ripple carries between the adders. Most techniques used in the combinational multiplier depend on the paper-and-pencil shift-and-add (PPSA) algorithm, which uses ripple carry adder architecture. This paper proposes an architecture called Cell-based Carry-Save Combinational Multiplier (CCCM) that focuses on the propagation delay and area. Each row represents a carry-save adder. The carry outputs are passed to the next row. For validating the proposed architecture, 16x16 multiplication is performed and the overall improvement in the delay is 73.32 % while there is a 3.31 % reduction in the area.

Delay-efficient 4:3 counter design using two-bit reordering circuit for high-speed Wallace tree multiplier

“…A high-speed multiplier is possible to design by decreasing the delay incurred by the PPR stage. There are several multiplier types such as array multiplier (AM) [4], [5], carry save multiplier (CSM) [6], [7], Wallace tree multiplier (WTM) [8]- [10], Vedic multiplier (VM) [11]- [15] and many others [16], [17] comes under the category of combinational multipliers. Among all, WTM and VM are flexible in structure hence huge research is going on them.…”